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mainboard/google/reef: add memory SKU id support 

While the proto boards didn't have a memory SKU notion the
EVT boards do. Therefore, provide support for selecting the
proper memory SKU information based on the memory id straps.

This works on EVT boards because the pins used for the
strapping weren't used on proto. However, internal pullups
need to be enabled so that proto boards read the correct
id.

BUG=chrome-os-partner:54949
BRANCH=None
TEST=Built and used on reef for memory config.

Change-Id: I8653260e5d1b9adc83b78ea2770c683b72535e11
Signed-off-by: Aaron Durbin <adurbin@chromuim.org>
Reviewed-on: https://review.coreboot.org/15560
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin 2016-07-06 22:51:05 -05:00
parent 87579aee69
commit fe767a7dc0
2 changed files with 72 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/mainboard/google/reef/gpio.h
View File

@ -243,8 +243,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_98, UP_20K, DEEP), /* FST_SPI_CS1_B -- unused */
PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), /* FST_SPI_MOSI_IO0 */
PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */
PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- unused */
PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- unused */
PAD_CFG_GPI(GPIO_101, UP_20K, DEEP), /* FST_IO2 -- MEM_CONFIG0 */
PAD_CFG_GPI(GPIO_102, UP_20K, DEEP), /* FST_IO3 -- MEM_CONFIG1 */
PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */
/* SIO_SPI_0 - Used for FP */
@ -312,7 +312,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_37, UP_20K, DEEP), /* unused */
/* LPSS_UART[0:2] */
PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - unused */
PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - MEM_CONFIG2*/
/* Next 2 are straps. */
PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */
PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */
@ -320,7 +320,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* LPSS_UART1_RXD */
PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* LPSS_UART1_TXD */
PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* LPSS_UART1_RTS */
PAD_CFG_NF(GPIO_45, NATIVE, DEEP, NF1), /* LPSS_UART1_CTS */
PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */
PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */
PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* LPSS_UART2_TXD */
PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */
@ -346,5 +346,15 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */
};
/*
* The proto boards didn't have memory SKU pins, but the same ones can be
* utilized as post proto boards because the pins used were never connected
* or no peripheral utilized the signals on proto boards.
*/
#define MEM_CONFIG3 GPIO_45
#define MEM_CONFIG2 GPIO_38
#define MEM_CONFIG1 GPIO_102
#define MEM_CONFIG0 GPIO_101
#endif /* __ACPI__ */
#endif /* MAINBOARD_GPIO_H */

66
src/mainboard/google/reef/romstage.c
View File

@ -13,8 +13,10 @@
* GNU General Public License for more details.
*/
#include <gpio.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include "gpio.h"
static const struct lpddr4_swizzle_cfg board_swizzle = {
/* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
@ -60,15 +62,63 @@ static const struct lpddr4_swizzle_cfg board_swizzle = {
},
};
/*
* Proto boards didn't have a memory SKU id. The configuration pins use
* an internal weak pullup with stronger pulldowns for the 0 bits. As
* proto boards didn't use the memory SKU pins the SKU id reads as 4'b1111,
* i.e. 15.
*/
#define PROTO_SKU 15
static const struct lpddr4_sku skus[] = {
/* K4F6E304HB-MGCJ - both logical channels */
[0] = {
.speed = LP4_SPEED_2400,
.ch0_density = LP4_16Gb_DENSITY,
.ch1_density = LP4_16Gb_DENSITY,
},
/* K4F8E304HB-MGCJ - both logical channels */
[1] = {
.speed = LP4_SPEED_2400,
.ch0_density = LP4_8Gb_DENSITY,
.ch1_density = LP4_8Gb_DENSITY,
},
/* MT53B512M32D2NP-062WT:C - both logical channels */
[2] = {
.speed = LP4_SPEED_2400,
.ch0_density = LP4_16Gb_DENSITY,
.ch1_density = LP4_16Gb_DENSITY,
/* MT53B256M32D1NP-062 WT:C - both logical channels */
},
[3] = {
.speed = LP4_SPEED_2400,
.ch0_density = LP4_8Gb_DENSITY,
.ch1_density = LP4_8Gb_DENSITY,
},
/* K4F8E304HB-MGCH - both logical channels */
[PROTO_SKU] = {
.speed = LP4_SPEED_2400,
.ch0_density = LP4_8Gb_DENSITY,
.ch1_density = LP4_8Gb_DENSITY,
},
};
static const struct lpddr4_cfg lp4cfg = {
.skus = skus,
.num_skus = ARRAY_SIZE(skus),
.swizzle_config = &board_swizzle,
};
void mainboard_memory_init_params(struct FSPM_UPD *memupd)
{
struct FSP_M_CONFIG *cfg = &memupd->FspmConfig;
int mem_sku;
gpio_t pads[] = { MEM_CONFIG3, MEM_CONFIG2, MEM_CONFIG1, MEM_CONFIG0 };
/* Use a default 2400 speed. */
meminit_lpddr4(cfg, LP4_SPEED_2400);
/* Enable both logical channels with a 8Gb density. */
meminit_lpddr4_enable_channel(cfg, LP4_LCH0, LP4_8Gb_DENSITY,
&board_swizzle);
meminit_lpddr4_enable_channel(cfg, LP4_LCH1, LP4_8Gb_DENSITY,
&board_swizzle);
/*
* Read memory SKU id with internal pullups enabled to handle
* proto boards with no SKU id pins.
*/
mem_sku = gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
meminit_lpddr4_by_sku(&memupd->FspmConfig, &lp4cfg, mem_sku);
}