first cut
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson
parent
383f5f6897
commit
fe78c82c40
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@ -1,4 +1,3 @@
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#if 0
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/*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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@ -48,24 +47,16 @@
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* Base on the U-Boot Startup Code
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*
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* The processor starts at 0xfffffffc and the code is executed
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* from flash/rom.
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* in memory, but as long we don't jump around before relocating.
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* board_init lies at a quite high address and when the cpu has
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* jumped there, everything is ok.
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* This works because the cpu gives the FLASH (CS0) the whole
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* address space at startup, and board_init lies as a echo of
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* the flash somewhere up there in the memorymap.
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* from flash/rom.
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*
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* board_init will change CS0 to be positioned at the correct
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* address and (s)dram will be positioned at address 0
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* The purpose of this code is:
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* - initalize the processor to a known state
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* - turn on the I cache so things execute at a reasonable speed
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* - set up a temporary stack in D cache
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*/
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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.globl _start
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_start:
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#include "ppc4xx.h"
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/*****************************************************************************/
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addi r4,r0,0x0000
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mtspr sgr,r4
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mtspr dcwr,r4
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@ -76,675 +67,49 @@ _start:
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addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */
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oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */
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mtmsr r4 /* change MSR */
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addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
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/* dbsr is cleared by setting bits to 1) */
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addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in */
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/* the dbsr is cleared by setting */
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/* bits to 1) */
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mtdbsr r4 /* clear/reset the dbsr */
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/*----------------------------------------------------------------------- */
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/* Invalidate I and D caches. Enable I cache for defined memory regions */
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/* to speed things up. Leave the D cache disabled for now. It will be */
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/* enabled/left disabled later based on user selected menu options. */
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/* Be aware that the I cache may be disabled later based on the menu */
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/* options as well. See miscLib/main.c. */
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/*----------------------------------------------------------------------- */
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/*
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* Invalidate I and D caches. Enable I cache for defined memory
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* regions to speed things up. Enable D cache for use as
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* temporary memory until real memory is enabled.
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*/
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bl invalidate_icache
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bl invalidate_dcache
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/*----------------------------------------------------------------------- */
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/* Enable two 128MB cachable regions. */
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/*----------------------------------------------------------------------- */
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addis r4,r0,0x8000
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/*
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* Enable two 128MB cachable instruction regions
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*
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* 0x00000000 - 0x07FFFFFF
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* 0xF8000000 - 0xFFFFFFFF
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*/
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lis r4,0x8000
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addi r4,r4,0x0001
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mticcr r4 /* instruction cache */
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mticcr r4 /* instruction cache enable */
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isync
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addis r4,r0,0x0000
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addi r4,r4,0x0000
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mtdccr r4 /* data cache */
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/*
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* Enable dcache region containing DCACHE_RAM_BASE
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* and set region to write-back
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*/
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#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
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/*----------------------------------------------------------------------- */
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/* Tune the speed and size for flash CS0 */
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/*----------------------------------------------------------------------- */
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bl ext_bus_cntlr_init
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#endif
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lis r4, DCACHE_RAM_BASE@ha
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addi r4, r4, DCACHE_RAM_BASE@l
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srwi r4, r4, 27
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li r0, 1
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slw r4, r0, r4
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nor r0, r4, r4
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mtdcr dcwr, r0 /* data cache write-back */
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mtdccr r4 /* data cache enable */
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sync
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#if defined(CONFIG_405EP)
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/*----------------------------------------------------------------------- */
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/* DMA Status, clear to come up clean */
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/*----------------------------------------------------------------------- */
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addis r3,r0, 0xFFFF /* Clear all existing DMA status */
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ori r3,r3, 0xFFFF
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mtdcr dmasr, r3
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bl ppc405ep_init /* do ppc405ep specific init */
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#endif /* CONFIG_405EP */
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/*----------------------------------------------------------------------- */
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/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
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/*----------------------------------------------------------------------- */
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#ifdef CFG_INIT_DCACHE_CS
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/*----------------------------------------------------------------------- */
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/* Memory Bank x (nothingness) initialization 1GB+64MEG */
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/* used as temporary stack pointer for stage0 */
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/*----------------------------------------------------------------------- */
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li r4,PBxAP
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mtdcr ebccfga,r4
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lis r4,0x0380
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ori r4,r4,0x0480
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mtdcr ebccfgd,r4
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addi r4,0,PBxCR
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mtdcr ebccfga,r4
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lis r4,0x400D
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ori r4,r4,0xa000
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mtdcr ebccfgd,r4
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/* turn on data chache for this region */
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lis r4,0x0080
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mtdccr r4
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/* set stack pointer and clear stack to known value */
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lis r1,CFG_INIT_RAM_ADDR@h
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ori r1,r1,CFG_INIT_SP_OFFSET@l
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li r4,2048 /* we store 2048 words to stack */
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mtctr r4
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lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */
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ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
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lis r4,0xdead /* we store 0xdeaddead in the stack */
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ori r4,r4,0xdead
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..stackloop:
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stwu r4,-4(r2)
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bdnz ..stackloop
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li r0, 0 /* Make room for stack frame header and */
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stwu r0, -4(r1) /* clear final stack frame so that */
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stwu r0, -4(r1) /* stack backtraces terminate cleanly */
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/*
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* Set up a dummy frame to store reset vector as return address.
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* this causes stack underflow to reset board.
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*/
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stwu r1, -8(r1) /* Save back chain and move SP */
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addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
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ori r0, r0, RESET_VECTOR@l
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stwu r1, -8(r1) /* Save back chain and move SP */
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stw r0, +12(r1) /* Save return addr (underflow vect) */
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#endif /* CFG_INIT_DCACHE_CS */
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/*----------------------------------------------------------------------- */
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/* Initialize SDRAM Controller */
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/*----------------------------------------------------------------------- */
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bl sdram_init
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/*
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* Setup temporary stack pointer only for boards
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* that do not use SDRAM SPD I2C stuff since it
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* is already initialized to use DCACHE or OCM
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* stacks.
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*/
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#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
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lis r1, CFG_INIT_RAM_ADDR@h
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ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
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li r0, 0 /* Make room for stack frame header and */
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stwu r0, -4(r1) /* clear final stack frame so that */
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stwu r0, -4(r1) /* stack backtraces terminate cleanly */
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/*
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* Set up a dummy frame to store reset vector as return address.
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* this causes stack underflow to reset board.
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*/
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stwu r1, -8(r1) /* Save back chain and move SP */
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lis r0, RESET_VECTOR@h /* Address of reset vector */
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ori r0, r0, RESET_VECTOR@l
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stwu r1, -8(r1) /* Save back chain and move SP */
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stw r0, +12(r1) /* Save return addr (underflow vect) */
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#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
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GET_GOT /* initialize GOT access */
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bl cpu_init_f /* run low-level CPU init code (from Flash) */
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/* NEVER RETURNS! */
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bl board_init_f /* run first part of init code (from Flash) */
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/* Cache functions.
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*/
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invalidate_icache:
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iccci r0,r0 /* for 405, iccci invalidates the */
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blr /* entire I cache */
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invalidate_dcache:
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addi r6,0,0x0000 /* clear GPR 6 */
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/* Do loop for # of dcache congruence classes. */
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addi r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
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/* NOTE: dccci invalidates both */
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mtctr r7 /* ways in the D cache */
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..dcloop:
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dccci 0,r6 /* invalidate line */
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addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
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bdnz ..dcloop
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blr
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flush_dcache:
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addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
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ori r9,r9,0x8000
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mfmsr r12 /* save msr */
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andc r9,r12,r9
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mtmsr r9 /* disable EE and CE */
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addi r10,r0,0x0001 /* enable data cache for unused memory */
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mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */
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or r10,r10,r9 /* bit 31 in dccr */
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mtdccr r10
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/* do loop for # of congruence classes. */
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addi r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
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addi r11,r0,(CFG_DCACHE_SIZE / 2) /* D cache set size - 2 way sets */
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mtctr r10
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addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
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add r11,r10,r11 /* add to get to other side of cache line */
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..flush_dcache_loop:
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lwz r3,0(r10) /* least recently used side */
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lwz r3,0(r11) /* the other side */
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dccci r0,r11 /* invalidate both sides */
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addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */
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addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */
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bdnz ..flush_dcache_loop
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sync /* allow memory access to complete */
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mtdccr r9 /* restore dccr */
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mtmsr r12 /* restore msr */
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blr
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.globl icache_enable
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icache_enable:
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mflr r8
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bl invalidate_icache
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mtlr r8
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isync
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addis r3,r0, 0x8000 /* set bit 0 */
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mticcr r3
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blr
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.globl icache_disable
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icache_disable:
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addis r3,r0, 0x0000 /* clear bit 0 */
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mticcr r3
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isync
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blr
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.globl icache_status
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icache_status:
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mficcr r3
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srwi r3, r3, 31 /* >>31 => select bit 0 */
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blr
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.globl dcache_enable
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dcache_enable:
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mflr r8
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bl invalidate_dcache
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mtlr r8
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isync
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addis r3,r0, 0x8000 /* set bit 0 */
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mtdccr r3
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blr
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.globl dcache_disable
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dcache_disable:
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mflr r8
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bl flush_dcache
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mtlr r8
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addis r3,r0, 0x0000 /* clear bit 0 */
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mtdccr r3
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blr
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.globl dcache_status
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dcache_status:
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mfdccr r3
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srwi r3, r3, 31 /* >>31 => select bit 0 */
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blr
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.globl get_pvr
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get_pvr:
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mfspr r3, PVR
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blr
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#if !defined(CONFIG_440)
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.globl wr_pit
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wr_pit:
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mtspr pit, r3
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blr
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#endif
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.globl wr_tcr
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wr_tcr:
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mtspr tcr, r3
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: ppcDcbf */
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/* Description: Data Cache block flush */
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/* Input: r3 = effective address */
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/* Output: none. */
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/*------------------------------------------------------------------------------- */
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.globl ppcDcbf
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ppcDcbf:
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dcbf r0,r3
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: ppcDcbi */
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/* Description: Data Cache block Invalidate */
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/* Input: r3 = effective address */
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/* Output: none. */
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/*------------------------------------------------------------------------------- */
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.globl ppcDcbi
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ppcDcbi:
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dcbi r0,r3
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blr
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/*------------------------------------------------------------------------------- */
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/* Function: ppcSync */
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/* Description: Processor Synchronize */
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/* Input: none. */
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/* Output: none. */
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/*------------------------------------------------------------------------------- */
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.globl ppcSync
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ppcSync:
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sync
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blr
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/*------------------------------------------------------------------------------*/
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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* r3 = dest
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* r4 = src
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* r5 = length in bytes
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* r6 = cachelinesize
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*/
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.globl relocate_code
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relocate_code:
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mr r1, r3 /* Set new stack pointer */
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mr r9, r4 /* Save copy of Init Data pointer */
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mr r10, r5 /* Save copy of Destination Address */
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mr r3, r5 /* Destination Address */
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lis r4, CFG_MONITOR_BASE@h /* Source Address */
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ori r4, r4, CFG_MONITOR_BASE@l
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lwz r5, GOT(__init_end)
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sub r5, r5, r4
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li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
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/*
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* Fix GOT pointer:
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*
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* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
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*
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* Offset:
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*/
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sub r15, r10, r4
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/* First our own GOT */
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add r14, r14, r15
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/* the the one used by the C code */
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add r30, r30, r15
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/*
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* Now relocate code
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*/
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cmplw cr1,r3,r4
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addi r0,r5,3
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srwi. r0,r0,2
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beq cr1,4f /* In place copy is not necessary */
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beq 7f /* Protect against 0 count */
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mtctr r0
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bge cr1,2f
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la r8,-4(r4)
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la r7,-4(r3)
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1: lwzu r0,4(r8)
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stwu r0,4(r7)
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bdnz 1b
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b 4f
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2: slwi r0,r0,2
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add r8,r4,r0
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add r7,r3,r0
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3: lwzu r0,-4(r8)
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stwu r0,-4(r7)
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bdnz 3b
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/*
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* Now flush the cache: note that we must start from a cache aligned
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* address. Otherwise we might miss one cache line.
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*/
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4: cmpwi r6,0
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add r5,r3,r5
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beq 7f /* Always flush prefetch queue in any case */
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subi r0,r6,1
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andc r3,r3,r0
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mr r4,r3
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5: dcbst 0,r4
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add r4,r4,r6
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cmplw r4,r5
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blt 5b
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sync /* Wait for all dcbst to complete on bus */
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mr r4,r3
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6: icbi 0,r4
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add r4,r4,r6
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cmplw r4,r5
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blt 6b
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7: sync /* Wait for all icbi to complete on bus */
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isync
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/*
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* We are done. Do not return, instead branch to second part of board
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* initialization, now running from RAM.
|
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*/
|
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addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
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mtlr r0
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blr /* NEVER RETURNS! */
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in_ram:
|
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||||
/*
|
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* Relocation Function, r14 point to got2+0x8000
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*
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* Adjust got2 pointers, no need to check for 0, this code
|
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* already puts a few entries in the table.
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*/
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li r0,__got2_entries@sectoff@l
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la r3,GOT(_GOT2_TABLE_)
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lwz r11,GOT(_GOT2_TABLE_)
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mtctr r0
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sub r11,r3,r11
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addi r3,r3,-4
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1: lwzu r0,4(r3)
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add r0,r0,r11
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stw r0,0(r3)
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||||
bdnz 1b
|
||||
|
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/*
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||||
* Now adjust the fixups and the pointers to the fixups
|
||||
* in case we need to move ourselves again.
|
||||
*/
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||||
2: li r0,__fixup_entries@sectoff@l
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lwz r3,GOT(_FIXUP_TABLE_)
|
||||
cmpwi r0,0
|
||||
mtctr r0
|
||||
addi r3,r3,-4
|
||||
beq 4f
|
||||
3: lwzu r4,4(r3)
|
||||
lwzux r0,r4,r11
|
||||
add r0,r0,r11
|
||||
stw r10,0(r3)
|
||||
stw r0,0(r4)
|
||||
bdnz 3b
|
||||
4:
|
||||
clear_bss:
|
||||
/*
|
||||
* Now clear BSS segment
|
||||
*/
|
||||
lwz r3,GOT(__bss_start)
|
||||
lwz r4,GOT(_end)
|
||||
|
||||
cmplw 0, r3, r4
|
||||
beq 6f
|
||||
|
||||
li r0, 0
|
||||
5:
|
||||
stw r0, 0(r3)
|
||||
addi r3, r3, 4
|
||||
cmplw 0, r3, r4
|
||||
bne 5b
|
||||
6:
|
||||
|
||||
mr r3, r9 /* Init Data pointer */
|
||||
mr r4, r10 /* Destination Address */
|
||||
bl board_init_r
|
||||
|
||||
/*
|
||||
* Copy exception vector code to low memory
|
||||
*
|
||||
* r3: dest_addr
|
||||
* r7: source address, r8: end address, r9: target address
|
||||
*/
|
||||
.globl trap_init
|
||||
trap_init:
|
||||
lwz r7, GOT(_start)
|
||||
lwz r8, GOT(_end_of_vectors)
|
||||
|
||||
li r9, 0x100 /* reset vector always at 0x100 */
|
||||
|
||||
cmplw 0, r7, r8
|
||||
bgelr /* return if r7>=r8 - just in case */
|
||||
|
||||
mflr r4 /* save link register */
|
||||
1:
|
||||
lwz r0, 0(r7)
|
||||
stw r0, 0(r9)
|
||||
addi r7, r7, 4
|
||||
addi r9, r9, 4
|
||||
cmplw 0, r7, r8
|
||||
bne 1b
|
||||
|
||||
/*
|
||||
* relocate `hdlr' and `int_return' entries
|
||||
*/
|
||||
li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
|
||||
li r8, Alignment - _start + EXC_OFF_SYS_RESET
|
||||
2:
|
||||
bl trap_reloc
|
||||
addi r7, r7, 0x100 /* next exception vector */
|
||||
cmplw 0, r7, r8
|
||||
blt 2b
|
||||
|
||||
li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
|
||||
bl trap_reloc
|
||||
|
||||
li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
|
||||
bl trap_reloc
|
||||
|
||||
li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
|
||||
li r8, SystemCall - _start + EXC_OFF_SYS_RESET
|
||||
3:
|
||||
bl trap_reloc
|
||||
addi r7, r7, 0x100 /* next exception vector */
|
||||
cmplw 0, r7, r8
|
||||
blt 3b
|
||||
|
||||
li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
|
||||
li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
|
||||
4:
|
||||
bl trap_reloc
|
||||
addi r7, r7, 0x100 /* next exception vector */
|
||||
cmplw 0, r7, r8
|
||||
blt 4b
|
||||
|
||||
mtlr r4 /* restore link register */
|
||||
blr
|
||||
|
||||
/*
|
||||
* Function: relocate entries for one exception vector
|
||||
*/
|
||||
trap_reloc:
|
||||
lwz r0, 0(r7) /* hdlr ... */
|
||||
add r0, r0, r3 /* ... += dest_addr */
|
||||
stw r0, 0(r7)
|
||||
|
||||
lwz r0, 4(r7) /* int_return ... */
|
||||
add r0, r0, r3 /* ... += dest_addr */
|
||||
stw r0, 4(r7)
|
||||
|
||||
blr
|
||||
|
||||
|
||||
#ifdef CONFIG_405EP
|
||||
ppc405ep_init:
|
||||
/*
|
||||
!-----------------------------------------------------------------------
|
||||
! Check FPGA for PCI internal/external arbitration
|
||||
! If board is set to internal arbitration, update cpc0_pci
|
||||
!-----------------------------------------------------------------------
|
||||
*/
|
||||
addi r3,0,CPC0_PCI_HOST_CFG_EN
|
||||
#ifdef CONFIG_BUBINGA405EP
|
||||
addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
|
||||
ori r5,r5,FPGA_REG1@l
|
||||
lbz r5,0x0(r5) /* read to get PCI arb selection */
|
||||
andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
|
||||
beq ..pci_cfg_set /* if not set, then bypass reg write*/
|
||||
#endif
|
||||
ori r3,r3,CPC0_PCI_ARBIT_EN
|
||||
..pci_cfg_set:
|
||||
mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
|
||||
|
||||
/*
|
||||
!-----------------------------------------------------------------------
|
||||
! Check to see if chip is in bypass mode.
|
||||
! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
|
||||
! CPU reset Otherwise, skip this step and keep going.
|
||||
! Note: Running BIOS in bypass mode is not supported since PLB speed
|
||||
! will not be fast enough for the SDRAM (min 66MHz)
|
||||
!-----------------------------------------------------------------------
|
||||
*/
|
||||
mfdcr r5, CPC0_PLLMR1
|
||||
rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
|
||||
cmpi cr0,0,r4,0x1
|
||||
|
||||
beq pll_done /* if SSCS =b'1' then PLL has */
|
||||
/* already been set */
|
||||
/* and CPU has been reset */
|
||||
/* so skip to next section */
|
||||
|
||||
#ifdef CONFIG_BUBINGA405EP
|
||||
/*
|
||||
!-----------------------------------------------------------------------
|
||||
! Read NVRAM to get value to write in PLLMR.
|
||||
! If value has not been correctly saved, write default value
|
||||
! Default config values (assuming on-board 33MHz SYS_CLK) are above.
|
||||
! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
|
||||
!
|
||||
! WARNING: This code assumes the first three words in the nvram_t
|
||||
! structure in openbios.h. Changing the beginning of
|
||||
! the structure will break this code.
|
||||
!
|
||||
!-----------------------------------------------------------------------
|
||||
*/
|
||||
addis r3,0,NVRAM_BASE@h
|
||||
addi r3,r3,NVRAM_BASE@l
|
||||
|
||||
lwz r4, 0(r3)
|
||||
addis r5,0,NVRVFY1@h
|
||||
addi r5,r5,NVRVFY1@l
|
||||
cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
|
||||
bne ..no_pllset
|
||||
addi r3,r3,4
|
||||
lwz r4, 0(r3)
|
||||
addis r5,0,NVRVFY2@h
|
||||
addi r5,r5,NVRVFY2@l
|
||||
cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
|
||||
bne ..no_pllset
|
||||
addi r3,r3,8 /* Skip over conf_size */
|
||||
lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
|
||||
lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
|
||||
rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
|
||||
cmpi cr0,0,r5,1 /* See if PLL is locked */
|
||||
beq pll_write
|
||||
..no_pllset:
|
||||
#endif /* CONFIG_BUBINGA405EP */
|
||||
|
||||
addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
|
||||
ori r3,r3,PLLMR0_DEFAULT@l /* */
|
||||
addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
|
||||
ori r4,r4,PLLMR1_DEFAULT@l /* */
|
||||
|
||||
b pll_write /* Write the CPC0_PLLMR with new value */
|
||||
|
||||
pll_done:
|
||||
/*
|
||||
!-----------------------------------------------------------------------
|
||||
! Clear Soft Reset Register
|
||||
! This is needed to enable PCI if not booting from serial EPROM
|
||||
!-----------------------------------------------------------------------
|
||||
*/
|
||||
addi r3, 0, 0x0
|
||||
mtdcr CPC0_SRR, r3
|
||||
|
||||
addis r3,0,0x0010
|
||||
mtctr r3
|
||||
pci_wait:
|
||||
bdnz pci_wait
|
||||
|
||||
blr /* return to main code */
|
||||
|
||||
/*
|
||||
!-----------------------------------------------------------------------------
|
||||
! Function: pll_write
|
||||
! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
|
||||
! That is:
|
||||
! 1. Pll is first disabled (de-activated by putting in bypass mode)
|
||||
! 2. PLL is reset
|
||||
! 3. Clock dividers are set while PLL is held in reset and bypassed
|
||||
! 4. PLL Reset is cleared
|
||||
! 5. Wait 100us for PLL to lock
|
||||
! 6. A core reset is performed
|
||||
! Input: r3 = Value to write to CPC0_PLLMR0
|
||||
! Input: r4 = Value to write to CPC0_PLLMR1
|
||||
! Output r3 = none
|
||||
!-----------------------------------------------------------------------------
|
||||
*/
|
||||
pll_write:
|
||||
mfdcr r5, CPC0_UCR
|
||||
andis. r5,r5,0xFFFF
|
||||
ori r5,r5,0x0101 /* Stop the UART clocks */
|
||||
mtdcr CPC0_UCR,r5 /* Before changing PLL */
|
||||
|
||||
mfdcr r5, CPC0_PLLMR1
|
||||
rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
|
||||
mtdcr CPC0_PLLMR1,r5
|
||||
oris r5,r5,0x4000 /* Set PLL Reset */
|
||||
mtdcr CPC0_PLLMR1,r5
|
||||
|
||||
mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
|
||||
rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
|
||||
oris r5,r5,0x4000 /* Set PLL Reset */
|
||||
mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
|
||||
rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
|
||||
mtdcr CPC0_PLLMR1,r5
|
||||
|
||||
/*
|
||||
! Wait min of 100us for PLL to lock.
|
||||
! See CMOS 27E databook for more info.
|
||||
! At 200MHz, that means waiting 20,000 instructions
|
||||
*/
|
||||
addi r3,0,20000 /* 2000 = 0x4e20 */
|
||||
mtctr r3
|
||||
pll_wait:
|
||||
bdnz pll_wait
|
||||
|
||||
oris r5,r5,0x8000 /* Enable PLL */
|
||||
mtdcr CPC0_PLLMR1,r5 /* Engage */
|
||||
|
||||
/*
|
||||
* Reset CPU to guarantee timings are OK
|
||||
* Not sure if this is needed...
|
||||
*/
|
||||
addis r3,0,0x1000
|
||||
mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
|
||||
/* execution will continue from the poweron */
|
||||
/* vector of 0xfffffffc */
|
||||
#endif /* CONFIG_405EP */
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue