This patch is for AMD boards which can do the P state generation. This just
removes the ugly binary DSDT patching and all other related stuff. Stick to infrastructure in previous patch. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek
parent
7ad11e8d33
commit
fe849b2ff7
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@ -1,90 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* This file defines the processor and performance state capability
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* for each core in the system. It is included into the DSDT for each
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* core. It assumes that each core of the system has the same performance
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* characteristics.
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*/
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/*
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DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
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{
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Scope (\_PR) {
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Processor(CPU0,0,0x808,0x06) {
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Include ("cpstate.asl")
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}
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Processor(CPU1,1,0x0,0x0) {
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Include ("cpstate.asl")
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}
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Processor(CPU2,2,0x0,0x0) {
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Include ("cpstate.asl")
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}
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Processor(CPU3,3,0x0,0x0) {
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Include ("cpstate.asl")
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}
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}
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*/
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/*
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* 1. Get the CPUID to know what the version of the CPU is. (or see what powernow
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* reports)
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* 2. Find how many P-states the CPU supports, power and frequecy in each
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* P-states in 'Power and Thermal Data Sheet.' (PTDS)
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* 3. Go to BIOS and Kernel Developer's Guide (BKDG) and find Low FID Frequency
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* Table & High FID Frequency Table. Find Fid for each frequency.
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* 4. In PTDS, got the Voltage for each P-state. In table VID Code Voltages of BKDG,
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* find the VID for each Voltage.
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* Is that clear?
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*/
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/* P-state support: The maximum number of P-states supported by the */
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/* CPUs we'll use is 6. */
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Name(_PSS, Package(){
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/* The processor core clock PLL lock time is 2 us for AMD NPT Family 0Fh Processors.*/
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/* vst=100us*/
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/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x13<<6|0xD, 0x13<<6|0xD */
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/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x14<<6|0xC, 0x14<<6|0xC */
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/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x15<<6|0xA, 0x15<<6|0xA */
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/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x16<<6|0x8, 0x16<<6|0x8 */
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/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x1E<<6|0x0, 0x1E<<6|0x0 */
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/*
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* Package() {2100, 35000, 100, 7, 0xE8202CCD, 0x04CD},
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* Package() {2000, 30100, 100, 7, 0xE8202D0C, 0x050C},
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* Package() {1800, 26400, 100, 7, 0xE8202D4A, 0x054A},
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* Package() {1600, 23000, 100, 7, 0xE8202D88, 0x0588},
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* Package() { 800, 9400, 100, 7, 0xE8202F80, 0x0780},
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*/
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/*Use this tricky method to reserve 8 Pstates space*/
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Package() {0x1FFFFFFF, 0x2FFFFFFF, 0x3FFFFFFF, 0x4FFFFFFF, 0x5FFFFFFF, 0x6FFFFFFF},
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Package() {0x7FFFFFFF, 0x8FFFFFFF, 0x9FFFFFFF, 0xAFFFFFFF, 0xBFFFFFFF, 0xCFFFFFFF},
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Package() {0xDFFFFFFF, 0xEFFFFFFF, 0x1FFFFFFF, 0x2FFFFFFF, 0x3FFFFFFF, 0x4FFFFFFF},
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Package() {0x5FFFFFFF, 0x6FFFFFFF, 0x7FFFFFFF, 0x8FFFFFFF, 0x9FFFFFFF, 0xAFFFFFFF},
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Package() {0xBFFFFFFF, 0xCFFFFFFF, 0xDFFFFFFF, 0xEFFFFFFF, 0x1FFFFFFF, 0x2FFFFFFF},
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Package() {0x3FFFFFFF, 0x4FFFFFFF, 0x5FFFFFFF, 0x6FFFFFFF, 0x7FFFFFFF, 0x8FFFFFFF},
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Package() {0x9FFFFFFF, 0xAFFFFFFF, 0xBFFFFFFF, 0xCFFFFFFF, 0xDFFFFFFF, 0xEFFFFFFF},
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Package() {0x1FFFFFFF, 0x2FFFFFFF, 0x3FFFFFFF, 0x4FFFFFFF, 0x5FFFFFFF, 0x6FFFFFFF},
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})
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Name(_PCT, Package(){
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ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
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ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
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})
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Method(_PPC, 0){
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Return(0)
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}
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@ -54,48 +54,6 @@ DefinitionBlock (
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Name(UOM8, 6)
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Name(UOM9, 6)
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/*
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* Processor Object
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*
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*/
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Scope (\_PR) { /* define processor scope */
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Processor(
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CPU0, /* name space name */
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0, /* Unique number for this processor */
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0x808, /* PBLK system I/O address !hardcoded! */
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0x06 /* PBLKLEN for boot processor */
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) {
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Include ("cpstate.asl")
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}
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Processor(
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CPU1, /* name space name */
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1, /* Unique number for this processor */
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0x0000, /* PBLK system I/O address !hardcoded! */
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0x00 /* PBLKLEN for boot processor */
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) {
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Include ("cpstate.asl")
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}
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Processor(
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CPU2, /* name space name */
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2, /* Unique number for this processor */
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0x0000, /* PBLK system I/O address !hardcoded! */
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0x00 /* PBLKLEN for boot processor */
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) {
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Include ("cpstate.asl")
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}
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Processor(
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CPU3, /* name space name */
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3, /* Unique number for this processor */
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0x0000, /* PBLK system I/O address !hardcoded! */
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0x00 /* PBLKLEN for boot processor */
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) {
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Include ("cpstate.asl")
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}
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} /* End _PR scope */
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/* Some global data */
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Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
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Name(OSV, Ones) /* Assume nothing */
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@ -27,6 +27,9 @@
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#include <cpu/amd/amdk8_sysconf.h>
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#include <../../../northbridge/amd/amdk8/amdk8_acpi.h>
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#include <arch/cpu.h>
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#include <cpu/amd/model_fxx_powernow.h>
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extern u16 pm_base;
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#define DUMP_ACPI_TABLES 0
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@ -120,476 +123,9 @@ void update_ssdtx(void *ssdtx, int i)
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}
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/*
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* Details about this algorithm , refert to BDKG 10.5.1
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* Two parts are included, the another is the DSDT reconstruction process
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*/
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u32 pstates_algorithm(acpi_header_t * dsdt)
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{
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u8 processor_brand[49];
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u32 *v;
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struct cpuid_result cpuid1;
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struct power_limit_encoding {
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u8 socket_type;
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u8 cmp_cap;
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u8 pwr_lmt;
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u32 power_limit;
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};
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u8 Max_fid, Max_vid, Start_fid, Start_vid, Min_fid, Min_vid;
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u16 Max_feq;
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u8 Pstate_fid[10];
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u16 Pstate_feq[10];
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u8 Pstate_vid[10];
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u32 Pstate_power[10];
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u32 Pstate_volt[10];
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u8 PstateStep, PstateStep_coef;
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u8 IntPstateSup;
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u8 Pstate_num;
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u16 Cur_feq;
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u8 Cur_fid;
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u8 cmp_cap, pwr_lmt;
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u32 power_limit = 0;
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u8 index;
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u32 i, j;
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u32 processor_length, scope_length;
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msr_t msr;
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u8 *dsdt_pointer;
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u8 *pointer1;
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u8 *pointer2;
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u8 byte_index;
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u32 old_dsdt_length, new_dsdt_length;
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u32 corefeq, power, transitionlatency, busmasterlatency, control,
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status;
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u32 new_package_length;
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u8 sum, checksum;
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u32 fid_multiplier;
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static struct power_limit_encoding TDP[20] = {
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{0x11, 0x0, 0x8, 62},
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{0x11, 0x1, 0x8, 89},
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{0x11, 0x1, 0xa, 103},
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{0x11, 0x1, 0xc, 125},
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{0x11, 0x0, 0x2, 15},
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{0x11, 0x0, 0x4, 35},
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{0x11, 0x1, 0x2, 35},
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{0x11, 0x0, 0x5, 45},
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{0x11, 0x1, 0x7, 76},
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{0x11, 0x1, 0x6, 65},
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{0x11, 0x1, 0x8, 89},
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{0x11, 0x0, 0x1, 8},
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{0x11, 0x1, 0x1, 22},
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{0x12, 0x0, 0x6, 25},
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{0x12, 0x0, 0x1, 8},
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{0x12, 0x0, 0x2, 9},
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{0x12, 0x0, 0x4, 15},
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{0x12, 0x0, 0xc, 35},
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{0x12, 0x1, 0xc, 35},
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{0x12, 0x1, 0x4, 20}
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};
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/* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */
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cpuid1 = cpuid(0x80000002);
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v = (u32 *) processor_brand;
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v[0] = cpuid1.eax;
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v[1] = cpuid1.ebx;
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v[2] = cpuid1.ecx;
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v[3] = cpuid1.edx;
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cpuid1 = cpuid(0x80000003);
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v[4] = cpuid1.eax;
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v[5] = cpuid1.ebx;
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v[6] = cpuid1.ecx;
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v[7] = cpuid1.edx;
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cpuid1 = cpuid(0x80000004);
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v[8] = cpuid1.eax;
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v[9] = cpuid1.ebx;
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v[10] = cpuid1.ecx;
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v[11] = cpuid1.edx;
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processor_brand[48] = 0;
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printk_info("processor_brand=%s\n", processor_brand);
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/*
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* Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
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* socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1
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* cmp_cap : 0x0 SingleCore ; 0x1 DualCore
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*/
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printk_info("Pstates Algorithm ...\n");
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cmp_cap =
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(pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) &
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0x3000) >> 12;
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cpuid1 = cpuid(0x80000001);
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pwr_lmt = ((cpuid1.ebx & 0x1C0) >> 5) | ((cpuid1.ebx & 0x4000) >> 14);
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for (index = 0; index <= sizeof(TDP) / sizeof(TDP[0]); index++)
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if (TDP[index].socket_type == CPU_SOCKET_TYPE &&
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TDP[index].cmp_cap == cmp_cap &&
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TDP[index].pwr_lmt == pwr_lmt) {
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power_limit = TDP[index].power_limit;
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}
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/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
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cpuid1 = cpuid(0x80000007);
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if ((cpuid1.edx & 0x6) != 0x6) {
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printk_info("No valid set of P-states\n");
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return 0;
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}
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msr = rdmsr(0xc0010042);
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Max_fid = (msr.lo & 0x3F0000) >> 16;
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Start_fid = (msr.lo & 0x3F00) >> 8;
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Max_vid = (msr.hi & 0x3F0000) >> 16;
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Start_vid = (msr.hi & 0x3F00) >> 8;
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PstateStep = (msr.hi & 0x1000000) >> 24;
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IntPstateSup = (msr.hi & 0x20000000) >> 29;
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/*
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* The P1...P[Min+1] VID need PstateStep to calculate
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* P[N] = P[N-1]VID + 2^PstateStep
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* PstateStep_coef = 2^PstateStep
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*/
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if (PstateStep == 0)
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PstateStep_coef = 1;
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else
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PstateStep_coef = 2;
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if (IntPstateSup == 0) {
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printk_info("No intermediate P-states are supported\n");
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return 0;
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}
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/* Get the multipier of the fid frequency */
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/*
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* Fid multiplier is always 100 revF and revG.
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*/
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fid_multiplier = 100;
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/*
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* Formula1: CPUFreq = FID * fid_multiplier + 800
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* Formula2: CPUVolt = 1550 - VID * 25 (mv)
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* Formula3: Power = (PwrLmt * P[N]Frequency*(P[N]Voltage^2))/(P[0]Frequency * P[0]Voltage^2))
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*/
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/* Construct P0(P[Max]) state */
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Pstate_num = 0;
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Max_feq = Max_fid * fid_multiplier + 800;
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if (Max_fid == 0x2A && Max_vid != 0x0) {
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Min_fid = 0x2;
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Pstate_fid[0] = Start_fid + 0xA; /* Start Frequency + 1GHz */
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Pstate_feq[0] = Pstate_fid[0] * fid_multiplier + 800;
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Min_vid = Start_vid;
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Pstate_vid[0] = Max_vid + 0x2; /* Maximum Voltage - 50mV */
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Pstate_volt[0] = 1550 - Pstate_vid[0] * 25;
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Pstate_power[0] = power_limit * 1000; /* mw */
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Pstate_num++;
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} else {
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Min_fid = Start_fid;
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Pstate_fid[0] = Max_fid;
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Pstate_feq[0] = Max_feq;
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Min_vid = Start_vid;
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Pstate_vid[0] = Max_vid + 0x2;
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Pstate_volt[0] = 1550 - Pstate_vid[0] * 25;
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Pstate_power[0] = power_limit * 1000; /* mw */
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Pstate_num++;
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}
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Cur_feq = Max_feq;
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Cur_fid = Max_fid;
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/* Construct P1 state */
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if (((Max_fid & 0x1) != 0) && ((Max_fid - 0x1) >= (Min_fid + 0x8))) { /* odd value */
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Pstate_fid[1] = Max_fid - 0x1;
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Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
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Cur_fid = Pstate_fid[1];
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Cur_feq = Pstate_feq[1];
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if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* odd value */
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Pstate_vid[1] = Pstate_vid[0] + 0x1;
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Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
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Pstate_power[1] =
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(unsigned long long)Pstate_power[0] *
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Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
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(Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
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}
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if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* even value */
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Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
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Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
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Pstate_power[1] =
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(unsigned long long)Pstate_power[0] *
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Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
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(Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
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}
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Pstate_num++;
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}
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if (((Max_fid & 0x1) == 0) && ((Max_fid - 0x2) >= (Min_fid + 0x8))) { /* even value */
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Pstate_fid[1] = Max_fid - 0x2;
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Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
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Cur_fid = Pstate_fid[1];
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Cur_feq = Pstate_feq[1];
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if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* odd value */
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Pstate_vid[1] = Pstate_vid[0] + 0x1;
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Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
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Pstate_power[1] =
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(unsigned long long)Pstate_power[0] *
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Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
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(Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
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}
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if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* even value */
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Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
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Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
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Pstate_power[1] =
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(unsigned long long)Pstate_power[0] *
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Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
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(Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
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}
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Pstate_num++;
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}
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/* Construct P2...P[Min-1] state */
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Cur_fid = Cur_fid - 0x2;
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Cur_feq = Cur_fid * fid_multiplier + 800;
|
||||
while (Cur_feq >= ((Min_fid * fid_multiplier) + 800) * 2) {
|
||||
Pstate_fid[Pstate_num] = Cur_fid;
|
||||
Pstate_feq[Pstate_num] =
|
||||
Pstate_fid[Pstate_num] * fid_multiplier + 800;
|
||||
Cur_fid = Cur_fid - 0x2;
|
||||
Cur_feq = Cur_fid * fid_multiplier + 800;
|
||||
if (Pstate_vid[Pstate_num - 1] >= Min_vid) {
|
||||
Pstate_vid[Pstate_num] = Pstate_vid[Pstate_num - 1];
|
||||
Pstate_volt[Pstate_num] = Pstate_volt[Pstate_num - 1];
|
||||
Pstate_power[Pstate_num] = Pstate_power[Pstate_num - 1];
|
||||
} else {
|
||||
Pstate_vid[Pstate_num] =
|
||||
Pstate_vid[Pstate_num - 1] + PstateStep_coef;
|
||||
Pstate_volt[Pstate_num] =
|
||||
1550 - Pstate_vid[Pstate_num] * 25;
|
||||
Pstate_power[Pstate_num] =
|
||||
(unsigned long long)Pstate_power[0] *
|
||||
Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
|
||||
Pstate_volt[Pstate_num] / (Pstate_feq[0] *
|
||||
Pstate_volt[0] *
|
||||
Pstate_volt[0]);
|
||||
}
|
||||
Pstate_num++;
|
||||
}
|
||||
|
||||
/* Constuct P[Min] State */
|
||||
if (Max_fid == 0x2A && Max_vid != 0x0) {
|
||||
Pstate_fid[Pstate_num] = 0x2;
|
||||
Pstate_feq[Pstate_num] =
|
||||
Pstate_fid[Pstate_num] * fid_multiplier + 800;
|
||||
Pstate_vid[Pstate_num] = Min_vid;
|
||||
Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
|
||||
Pstate_power[Pstate_num] =
|
||||
(unsigned long long)Pstate_power[0] *
|
||||
Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
|
||||
Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] *
|
||||
Pstate_volt[0]);
|
||||
Pstate_num++;
|
||||
} else {
|
||||
Pstate_fid[Pstate_num] = Start_fid;
|
||||
Pstate_feq[Pstate_num] =
|
||||
Pstate_fid[Pstate_num] * fid_multiplier + 800;
|
||||
Pstate_vid[Pstate_num] = Min_vid;
|
||||
Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
|
||||
Pstate_power[Pstate_num] =
|
||||
(unsigned long long)Pstate_power[0] *
|
||||
Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
|
||||
Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] *
|
||||
Pstate_volt[0]);
|
||||
Pstate_num++;
|
||||
}
|
||||
|
||||
/* Print Pstate freq,vid,volt,power */
|
||||
|
||||
for (index = 0; index < Pstate_num; index++) {
|
||||
printk_info("Pstate_freq[%d] = %dMHz\t", index,
|
||||
Pstate_feq[index]);
|
||||
printk_info("Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
|
||||
printk_info("Pstate_volt[%d] = %dmv\t", index,
|
||||
Pstate_volt[index]);
|
||||
printk_info("Pstate_power[%d] = %dmw\n", index,
|
||||
Pstate_power[index]);
|
||||
}
|
||||
|
||||
/*
|
||||
* Modify the DSDT Table to put the actural _PSS package
|
||||
* corefeq-->Pstate_feq[index]
|
||||
* power-->Pstate_power[index]
|
||||
* transitionlatency-->0x64
|
||||
* busmasterlatency-->0x7,
|
||||
* control--> 0xE8202800| Pstate_vid[index]<<6 | Pstate_fid[index]
|
||||
* status --> Pstate_vid[index]<<6 | Pstate_fid[index]
|
||||
* Get the _PSS control method Sig.
|
||||
*/
|
||||
|
||||
dsdt_pointer = (u8 *) dsdt;
|
||||
old_dsdt_length = dsdt->length;
|
||||
new_dsdt_length = old_dsdt_length;
|
||||
printk_info("DSDT reconstruction...\n");
|
||||
for (i = 0x20; i < new_dsdt_length; i++)
|
||||
if ((*(dsdt_pointer + i) == '_')
|
||||
&& (*(dsdt_pointer + i + 1) == 'P')
|
||||
&& (*(dsdt_pointer + i + 2) == 'S')
|
||||
&& (*(dsdt_pointer + i + 3) == 'S')) {
|
||||
|
||||
if ((*(dsdt_pointer + i + 4) !=
|
||||
0x12) | (*(dsdt_pointer + i + 5) !=
|
||||
0x4B) | (*(dsdt_pointer + i + 6) !=
|
||||
0x10)) {
|
||||
printk_info
|
||||
("Error:No _PSS package leader byte!\n");
|
||||
} else {
|
||||
new_package_length =
|
||||
0x10B - Defpkglength * (Maxpstate -
|
||||
Pstate_num);
|
||||
/* two Pstates length will larger than 63, so we need not worry about the length */
|
||||
if (new_package_length > 63) {
|
||||
*(dsdt_pointer + i + 5) =
|
||||
0x40 | (new_package_length & 0xf);
|
||||
*(dsdt_pointer + i + 6) =
|
||||
(new_package_length & 0xff0) >> 4;
|
||||
}
|
||||
*(dsdt_pointer + i + 7) = Pstate_num;
|
||||
}
|
||||
|
||||
if ((*(dsdt_pointer + i + 8) !=
|
||||
0x12) | (*(dsdt_pointer + i + 9) !=
|
||||
0x20) | (*(dsdt_pointer + i + 10) != 0x6))
|
||||
printk_info
|
||||
("Error:No package leader for the first Pstate!\n");
|
||||
for (index = 0; index < Pstate_num; index++) {
|
||||
corefeq = Pstate_feq[index];
|
||||
power = Pstate_power[index];
|
||||
transitionlatency = 0x64;
|
||||
busmasterlatency = 0x7;
|
||||
control =
|
||||
(0x3 << 30) | /* IRT */
|
||||
(0x2 << 28) | /* RVO */
|
||||
(0x1 << 27) | /* ExtType */
|
||||
(0x2 << 20) | /* PLL_LOCK_TIME */
|
||||
(0x0 << 18) | /* MVS */
|
||||
(0x5 << 11) | /* VST */
|
||||
(Pstate_vid[index] << 6) |
|
||||
Pstate_fid[index];
|
||||
status =
|
||||
(Pstate_vid[index] << 6) |
|
||||
Pstate_fid[index];
|
||||
for (byte_index = 0; byte_index < 4;
|
||||
byte_index++) {
|
||||
*(dsdt_pointer + i + 0xC +
|
||||
Defpkglength * index + byte_index) =
|
||||
corefeq >> (8 * byte_index);
|
||||
*(dsdt_pointer + i + 0xC +
|
||||
Defpkglength * index + 0x5 +
|
||||
byte_index) =
|
||||
power >> (8 * byte_index);
|
||||
*(dsdt_pointer + i + 0xC +
|
||||
Defpkglength * index + 0x5 * 2 +
|
||||
byte_index) =
|
||||
transitionlatency >> (8 * byte_index);
|
||||
*(dsdt_pointer + i + 0xC +
|
||||
Defpkglength * index + 0x5 * 3 +
|
||||
byte_index) =
|
||||
busmasterlatency >> (8 * byte_index);
|
||||
*(dsdt_pointer + i + 0xC +
|
||||
Defpkglength * index + 0x5 * 4 +
|
||||
byte_index) =
|
||||
control >> (8 * byte_index);
|
||||
*(dsdt_pointer + i + 0xC +
|
||||
Defpkglength * index + 0x5 * 5 +
|
||||
byte_index) =
|
||||
status >> (8 * byte_index);
|
||||
}
|
||||
}
|
||||
pointer1 =
|
||||
dsdt_pointer + i + 8 + Pstate_num * Defpkglength;
|
||||
pointer2 =
|
||||
dsdt_pointer + i + 8 + Maxpstate * Defpkglength;
|
||||
while (pointer2 < dsdt_pointer + new_dsdt_length) {
|
||||
*pointer1 = *pointer2;
|
||||
pointer1++;
|
||||
pointer2++;
|
||||
}
|
||||
/* Recalcute the DSDT length */
|
||||
new_dsdt_length =
|
||||
new_dsdt_length - Defpkglength * (Maxpstate -
|
||||
Pstate_num);
|
||||
|
||||
/* Search the first processor(CPUx) item and recalculate the processor length */
|
||||
for (j = 0; (dsdt_pointer + i - j) > dsdt_pointer; j++) {
|
||||
if ((*(dsdt_pointer + i - j) == 'C')
|
||||
&& (*(dsdt_pointer + i - j + 1) == 'P')
|
||||
&& (*(dsdt_pointer + i - j + 2) == 'U')) {
|
||||
processor_length =
|
||||
((*(dsdt_pointer + i - j - 1) << 4)
|
||||
| (*(dsdt_pointer + i - j - 2) &
|
||||
0xf));
|
||||
processor_length =
|
||||
processor_length -
|
||||
Defpkglength * (Maxpstate -
|
||||
Pstate_num);
|
||||
*(dsdt_pointer + i - j - 2) =
|
||||
(processor_length & 0xf) | 0x40;
|
||||
*(dsdt_pointer + i - j - 1) =
|
||||
(processor_length & 0xff0) >> 4;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Search the first scope(_PR_) item and recalculate the scope length */
|
||||
for (j = 0; (dsdt_pointer + i - j) > dsdt_pointer; j++) {
|
||||
if ((*(dsdt_pointer + i - j) == '_')
|
||||
&& (*(dsdt_pointer + i - j + 1) == 'P')
|
||||
&& (*(dsdt_pointer + i - j + 2) == 'R')
|
||||
&& (*(dsdt_pointer + i - j + 3) == '_')) {
|
||||
scope_length =
|
||||
((*(dsdt_pointer + i - j - 1) << 4)
|
||||
| (*(dsdt_pointer + i - j - 2) &
|
||||
0xf));
|
||||
scope_length =
|
||||
scope_length -
|
||||
Defpkglength * (Maxpstate -
|
||||
Pstate_num);
|
||||
*(dsdt_pointer + i - j - 2) =
|
||||
(scope_length & 0xf) | 0x40;
|
||||
*(dsdt_pointer + i - j - 1) =
|
||||
(scope_length & 0xff0) >> 4;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Recalculate the DSDT length and fill back to the table */
|
||||
*(dsdt_pointer + 0x4) = new_dsdt_length;
|
||||
*(dsdt_pointer + 0x5) = new_dsdt_length >> 8;
|
||||
|
||||
/*
|
||||
* Recalculate the DSDT checksum and fill back to the table
|
||||
* We must make sure the sum of the whole table is 0
|
||||
*/
|
||||
sum = 0;
|
||||
for (i = 0; i < new_dsdt_length; i++)
|
||||
if (i != 9)
|
||||
sum = sum + *(dsdt_pointer + i);
|
||||
checksum = 0x100 - sum;
|
||||
*(dsdt_pointer + 0x9) = checksum;
|
||||
|
||||
/*Check the DSDT Table */
|
||||
/*
|
||||
* printk_info("The new DSDT table length is %x\n", new_dsdt_length);
|
||||
* printk_info("Details is as below:\n");
|
||||
* for(i=0; i< new_dsdt_length; i++){
|
||||
* printk_info("%x\t",(unsigned char)*(dsdt_pointer+i));
|
||||
* if( ((i+1)&0x7) == 0x0)
|
||||
* printk_info("**0x%x**\n",i-7);
|
||||
*}
|
||||
*/
|
||||
|
||||
return 1;
|
||||
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) {
|
||||
k8acpi_write_vars();
|
||||
amd_model_fxx_generate_powernow(pm_base + 8, 6, 1);
|
||||
return (unsigned long) (acpigen_get_current());
|
||||
}
|
||||
|
||||
|
|
@ -717,11 +253,6 @@ unsigned long write_acpi_tables(unsigned long start)
|
|||
dsdt = (acpi_header_t *) current;
|
||||
memcpy((void *)dsdt, (void *)AmlCode,
|
||||
((acpi_header_t *) AmlCode)->length);
|
||||
if (!pstates_algorithm(dsdt))
|
||||
printk_debug("pstates_algorithm error!\n");
|
||||
else
|
||||
printk_debug("pstates_algorithm success.\n");
|
||||
|
||||
current += dsdt->length;
|
||||
printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length);
|
||||
/* FADT */
|
||||
|
|
|
|||
|
|
@ -1,90 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* This file defines the processor and performance state capability
|
||||
* for each core in the system. It is included into the DSDT for each
|
||||
* core. It assumes that each core of the system has the same performance
|
||||
* characteristics.
|
||||
*/
|
||||
/*
|
||||
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
|
||||
{
|
||||
Scope (\_PR) {
|
||||
Processor(CPU0,0,0x808,0x06) {
|
||||
Include ("cpstate.asl")
|
||||
}
|
||||
Processor(CPU1,1,0x0,0x0) {
|
||||
Include ("cpstate.asl")
|
||||
}
|
||||
Processor(CPU2,2,0x0,0x0) {
|
||||
Include ("cpstate.asl")
|
||||
}
|
||||
Processor(CPU3,3,0x0,0x0) {
|
||||
Include ("cpstate.asl")
|
||||
}
|
||||
}
|
||||
*/
|
||||
/*
|
||||
* 1. Get the CPUID to know what the version of the CPU is. (or see what powernow
|
||||
* reports)
|
||||
* 2. Find how many P-states the CPU supports, power and frequecy in each
|
||||
* P-states in 'Power and Thermal Data Sheet.' (PTDS)
|
||||
* 3. Go to BIOS and Kernel Developer's Guide (BKDG) and find Low FID Frequency
|
||||
* Table & High FID Frequency Table. Find Fid for each frequency.
|
||||
* 4. In PTDS, got the Voltage for each P-state. In table VID Code Voltages of BKDG,
|
||||
* find the VID for each Voltage.
|
||||
* Is that clear?
|
||||
*/
|
||||
|
||||
/* P-state support: The maximum number of P-states supported by the */
|
||||
/* CPUs we'll use is 6. */
|
||||
Name(_PSS, Package(){
|
||||
/* The processor core clock PLL lock time is 2 us for AMD NPT Family 0Fh Processors.*/
|
||||
/* vst=100us*/
|
||||
/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x13<<6|0xD, 0x13<<6|0xD */
|
||||
/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x14<<6|0xC, 0x14<<6|0xC */
|
||||
/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x15<<6|0xA, 0x15<<6|0xA */
|
||||
/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x16<<6|0x8, 0x16<<6|0x8 */
|
||||
/* 3<<31|2<<28|1<<27|2<<20|0<<18|5<<11|0x1E<<6|0x0, 0x1E<<6|0x0 */
|
||||
/*
|
||||
* Package() {2100, 35000, 100, 7, 0xE8202CCD, 0x04CD},
|
||||
* Package() {2000, 30100, 100, 7, 0xE8202D0C, 0x050C},
|
||||
* Package() {1800, 26400, 100, 7, 0xE8202D4A, 0x054A},
|
||||
* Package() {1600, 23000, 100, 7, 0xE8202D88, 0x0588},
|
||||
* Package() { 800, 9400, 100, 7, 0xE8202F80, 0x0780},
|
||||
*/
|
||||
/*Use this tricky method to reserve 8 Pstates space*/
|
||||
Package() {0x1FFFFFFF, 0x2FFFFFFF, 0x3FFFFFFF, 0x4FFFFFFF, 0x5FFFFFFF, 0x6FFFFFFF},
|
||||
Package() {0x7FFFFFFF, 0x8FFFFFFF, 0x9FFFFFFF, 0xAFFFFFFF, 0xBFFFFFFF, 0xCFFFFFFF},
|
||||
Package() {0xDFFFFFFF, 0xEFFFFFFF, 0x1FFFFFFF, 0x2FFFFFFF, 0x3FFFFFFF, 0x4FFFFFFF},
|
||||
Package() {0x5FFFFFFF, 0x6FFFFFFF, 0x7FFFFFFF, 0x8FFFFFFF, 0x9FFFFFFF, 0xAFFFFFFF},
|
||||
Package() {0xBFFFFFFF, 0xCFFFFFFF, 0xDFFFFFFF, 0xEFFFFFFF, 0x1FFFFFFF, 0x2FFFFFFF},
|
||||
Package() {0x3FFFFFFF, 0x4FFFFFFF, 0x5FFFFFFF, 0x6FFFFFFF, 0x7FFFFFFF, 0x8FFFFFFF},
|
||||
Package() {0x9FFFFFFF, 0xAFFFFFFF, 0xBFFFFFFF, 0xCFFFFFFF, 0xDFFFFFFF, 0xEFFFFFFF},
|
||||
Package() {0x1FFFFFFF, 0x2FFFFFFF, 0x3FFFFFFF, 0x4FFFFFFF, 0x5FFFFFFF, 0x6FFFFFFF},
|
||||
})
|
||||
|
||||
Name(_PCT, Package(){
|
||||
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
|
||||
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
|
||||
})
|
||||
|
||||
Method(_PPC, 0){
|
||||
Return(0)
|
||||
}
|
||||
|
|
@ -54,48 +54,6 @@ DefinitionBlock (
|
|||
Name(UOM8, 6)
|
||||
Name(UOM9, 6)
|
||||
|
||||
/*
|
||||
* Processor Object
|
||||
*
|
||||
*/
|
||||
Scope (\_PR) { /* define processor scope */
|
||||
Processor(
|
||||
CPU0, /* name space name */
|
||||
0, /* Unique number for this processor */
|
||||
0x808, /* PBLK system I/O address !hardcoded! */
|
||||
0x06 /* PBLKLEN for boot processor */
|
||||
) {
|
||||
Include ("cpstate.asl")
|
||||
}
|
||||
|
||||
Processor(
|
||||
CPU1, /* name space name */
|
||||
1, /* Unique number for this processor */
|
||||
0x0000, /* PBLK system I/O address !hardcoded! */
|
||||
0x00 /* PBLKLEN for boot processor */
|
||||
) {
|
||||
Include ("cpstate.asl")
|
||||
}
|
||||
|
||||
Processor(
|
||||
CPU2, /* name space name */
|
||||
2, /* Unique number for this processor */
|
||||
0x0000, /* PBLK system I/O address !hardcoded! */
|
||||
0x00 /* PBLKLEN for boot processor */
|
||||
) {
|
||||
Include ("cpstate.asl")
|
||||
}
|
||||
|
||||
Processor(
|
||||
CPU3, /* name space name */
|
||||
3, /* Unique number for this processor */
|
||||
0x0000, /* PBLK system I/O address !hardcoded! */
|
||||
0x00 /* PBLKLEN for boot processor */
|
||||
) {
|
||||
Include ("cpstate.asl")
|
||||
}
|
||||
} /* End _PR scope */
|
||||
|
||||
/* Some global data */
|
||||
Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
|
||||
Name(OSV, Ones) /* Assume nothing */
|
||||
|
|
|
|||
|
|
@ -27,6 +27,9 @@
|
|||
#include <cpu/amd/amdk8_sysconf.h>
|
||||
#include <../../../northbridge/amd/amdk8/amdk8_acpi.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/amd/model_fxx_powernow.h>
|
||||
|
||||
extern u16 pm_base;
|
||||
|
||||
#define DUMP_ACPI_TABLES 0
|
||||
|
||||
|
|
@ -120,476 +123,9 @@ void update_ssdtx(void *ssdtx, int i)
|
|||
|
||||
}
|
||||
|
||||
/*
|
||||
* Details about this algorithm , refert to BDKG 10.5.1
|
||||
* Two parts are included, the another is the DSDT reconstruction process
|
||||
*/
|
||||
u32 pstates_algorithm(acpi_header_t * dsdt)
|
||||
{
|
||||
u8 processor_brand[49];
|
||||
u32 *v;
|
||||
struct cpuid_result cpuid1;
|
||||
|
||||
struct power_limit_encoding {
|
||||
u8 socket_type;
|
||||
u8 cmp_cap;
|
||||
u8 pwr_lmt;
|
||||
u32 power_limit;
|
||||
};
|
||||
u8 Max_fid, Max_vid, Start_fid, Start_vid, Min_fid, Min_vid;
|
||||
u16 Max_feq;
|
||||
u8 Pstate_fid[10];
|
||||
u16 Pstate_feq[10];
|
||||
u8 Pstate_vid[10];
|
||||
u32 Pstate_power[10];
|
||||
u32 Pstate_volt[10];
|
||||
u8 PstateStep, PstateStep_coef;
|
||||
u8 IntPstateSup;
|
||||
u8 Pstate_num;
|
||||
u16 Cur_feq;
|
||||
u8 Cur_fid;
|
||||
u8 cmp_cap, pwr_lmt;
|
||||
u32 power_limit = 0;
|
||||
u8 index;
|
||||
u32 i, j;
|
||||
u32 processor_length, scope_length;
|
||||
msr_t msr;
|
||||
u8 *dsdt_pointer;
|
||||
u8 *pointer1;
|
||||
u8 *pointer2;
|
||||
u8 byte_index;
|
||||
u32 old_dsdt_length, new_dsdt_length;
|
||||
u32 corefeq, power, transitionlatency, busmasterlatency, control,
|
||||
status;
|
||||
u32 new_package_length;
|
||||
u8 sum, checksum;
|
||||
u32 fid_multiplier;
|
||||
static struct power_limit_encoding TDP[20] = {
|
||||
{0x11, 0x0, 0x8, 62},
|
||||
{0x11, 0x1, 0x8, 89},
|
||||
{0x11, 0x1, 0xa, 103},
|
||||
{0x11, 0x1, 0xc, 125},
|
||||
{0x11, 0x0, 0x2, 15},
|
||||
{0x11, 0x0, 0x4, 35},
|
||||
{0x11, 0x1, 0x2, 35},
|
||||
{0x11, 0x0, 0x5, 45},
|
||||
{0x11, 0x1, 0x7, 76},
|
||||
{0x11, 0x1, 0x6, 65},
|
||||
{0x11, 0x1, 0x8, 89},
|
||||
{0x11, 0x0, 0x1, 8},
|
||||
{0x11, 0x1, 0x1, 22},
|
||||
{0x12, 0x0, 0x6, 25},
|
||||
{0x12, 0x0, 0x1, 8},
|
||||
{0x12, 0x0, 0x2, 9},
|
||||
{0x12, 0x0, 0x4, 15},
|
||||
{0x12, 0x0, 0xc, 35},
|
||||
{0x12, 0x1, 0xc, 35},
|
||||
{0x12, 0x1, 0x4, 20}
|
||||
};
|
||||
|
||||
/* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */
|
||||
cpuid1 = cpuid(0x80000002);
|
||||
v = (u32 *) processor_brand;
|
||||
v[0] = cpuid1.eax;
|
||||
v[1] = cpuid1.ebx;
|
||||
v[2] = cpuid1.ecx;
|
||||
v[3] = cpuid1.edx;
|
||||
cpuid1 = cpuid(0x80000003);
|
||||
v[4] = cpuid1.eax;
|
||||
v[5] = cpuid1.ebx;
|
||||
v[6] = cpuid1.ecx;
|
||||
v[7] = cpuid1.edx;
|
||||
cpuid1 = cpuid(0x80000004);
|
||||
v[8] = cpuid1.eax;
|
||||
v[9] = cpuid1.ebx;
|
||||
v[10] = cpuid1.ecx;
|
||||
v[11] = cpuid1.edx;
|
||||
processor_brand[48] = 0;
|
||||
printk_info("processor_brand=%s\n", processor_brand);
|
||||
|
||||
/*
|
||||
* Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
|
||||
* socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1
|
||||
* cmp_cap : 0x0 SingleCore ; 0x1 DualCore
|
||||
*/
|
||||
printk_info("Pstates Algorithm ...\n");
|
||||
cmp_cap =
|
||||
(pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) &
|
||||
0x3000) >> 12;
|
||||
cpuid1 = cpuid(0x80000001);
|
||||
pwr_lmt = ((cpuid1.ebx & 0x1C0) >> 5) | ((cpuid1.ebx & 0x4000) >> 14);
|
||||
for (index = 0; index <= sizeof(TDP) / sizeof(TDP[0]); index++)
|
||||
if (TDP[index].socket_type == CPU_SOCKET_TYPE &&
|
||||
TDP[index].cmp_cap == cmp_cap &&
|
||||
TDP[index].pwr_lmt == pwr_lmt) {
|
||||
power_limit = TDP[index].power_limit;
|
||||
}
|
||||
|
||||
/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
|
||||
cpuid1 = cpuid(0x80000007);
|
||||
if ((cpuid1.edx & 0x6) != 0x6) {
|
||||
printk_info("No valid set of P-states\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
msr = rdmsr(0xc0010042);
|
||||
Max_fid = (msr.lo & 0x3F0000) >> 16;
|
||||
Start_fid = (msr.lo & 0x3F00) >> 8;
|
||||
Max_vid = (msr.hi & 0x3F0000) >> 16;
|
||||
Start_vid = (msr.hi & 0x3F00) >> 8;
|
||||
PstateStep = (msr.hi & 0x1000000) >> 24;
|
||||
IntPstateSup = (msr.hi & 0x20000000) >> 29;
|
||||
|
||||
/*
|
||||
* The P1...P[Min+1] VID need PstateStep to calculate
|
||||
* P[N] = P[N-1]VID + 2^PstateStep
|
||||
* PstateStep_coef = 2^PstateStep
|
||||
*/
|
||||
if (PstateStep == 0)
|
||||
PstateStep_coef = 1;
|
||||
else
|
||||
PstateStep_coef = 2;
|
||||
|
||||
if (IntPstateSup == 0) {
|
||||
printk_info("No intermediate P-states are supported\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Get the multipier of the fid frequency */
|
||||
/*
|
||||
* Fid multiplier is always 100 revF and revG.
|
||||
*/
|
||||
fid_multiplier = 100;
|
||||
|
||||
/*
|
||||
* Formula1: CPUFreq = FID * fid_multiplier + 800
|
||||
* Formula2: CPUVolt = 1550 - VID * 25 (mv)
|
||||
* Formula3: Power = (PwrLmt * P[N]Frequency*(P[N]Voltage^2))/(P[0]Frequency * P[0]Voltage^2))
|
||||
*/
|
||||
|
||||
/* Construct P0(P[Max]) state */
|
||||
Pstate_num = 0;
|
||||
Max_feq = Max_fid * fid_multiplier + 800;
|
||||
if (Max_fid == 0x2A && Max_vid != 0x0) {
|
||||
Min_fid = 0x2;
|
||||
Pstate_fid[0] = Start_fid + 0xA; /* Start Frequency + 1GHz */
|
||||
Pstate_feq[0] = Pstate_fid[0] * fid_multiplier + 800;
|
||||
Min_vid = Start_vid;
|
||||
Pstate_vid[0] = Max_vid + 0x2; /* Maximum Voltage - 50mV */
|
||||
Pstate_volt[0] = 1550 - Pstate_vid[0] * 25;
|
||||
Pstate_power[0] = power_limit * 1000; /* mw */
|
||||
Pstate_num++;
|
||||
} else {
|
||||
Min_fid = Start_fid;
|
||||
Pstate_fid[0] = Max_fid;
|
||||
Pstate_feq[0] = Max_feq;
|
||||
Min_vid = Start_vid;
|
||||
Pstate_vid[0] = Max_vid + 0x2;
|
||||
Pstate_volt[0] = 1550 - Pstate_vid[0] * 25;
|
||||
Pstate_power[0] = power_limit * 1000; /* mw */
|
||||
Pstate_num++;
|
||||
}
|
||||
|
||||
Cur_feq = Max_feq;
|
||||
Cur_fid = Max_fid;
|
||||
/* Construct P1 state */
|
||||
if (((Max_fid & 0x1) != 0) && ((Max_fid - 0x1) >= (Min_fid + 0x8))) { /* odd value */
|
||||
Pstate_fid[1] = Max_fid - 0x1;
|
||||
Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
|
||||
Cur_fid = Pstate_fid[1];
|
||||
Cur_feq = Pstate_feq[1];
|
||||
if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* odd value */
|
||||
Pstate_vid[1] = Pstate_vid[0] + 0x1;
|
||||
Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
|
||||
Pstate_power[1] =
|
||||
(unsigned long long)Pstate_power[0] *
|
||||
Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
|
||||
(Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
|
||||
}
|
||||
if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* even value */
|
||||
Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
|
||||
Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
|
||||
Pstate_power[1] =
|
||||
(unsigned long long)Pstate_power[0] *
|
||||
Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
|
||||
(Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
|
||||
}
|
||||
Pstate_num++;
|
||||
}
|
||||
|
||||
if (((Max_fid & 0x1) == 0) && ((Max_fid - 0x2) >= (Min_fid + 0x8))) { /* even value */
|
||||
Pstate_fid[1] = Max_fid - 0x2;
|
||||
Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
|
||||
Cur_fid = Pstate_fid[1];
|
||||
Cur_feq = Pstate_feq[1];
|
||||
if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* odd value */
|
||||
Pstate_vid[1] = Pstate_vid[0] + 0x1;
|
||||
Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
|
||||
Pstate_power[1] =
|
||||
(unsigned long long)Pstate_power[0] *
|
||||
Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
|
||||
(Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
|
||||
}
|
||||
if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* even value */
|
||||
Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
|
||||
Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
|
||||
Pstate_power[1] =
|
||||
(unsigned long long)Pstate_power[0] *
|
||||
Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
|
||||
(Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
|
||||
}
|
||||
|
||||
Pstate_num++;
|
||||
}
|
||||
|
||||
/* Construct P2...P[Min-1] state */
|
||||
Cur_fid = Cur_fid - 0x2;
|
||||
Cur_feq = Cur_fid * fid_multiplier + 800;
|
||||
while (Cur_feq >= ((Min_fid * fid_multiplier) + 800) * 2) {
|
||||
Pstate_fid[Pstate_num] = Cur_fid;
|
||||
Pstate_feq[Pstate_num] =
|
||||
Pstate_fid[Pstate_num] * fid_multiplier + 800;
|
||||
Cur_fid = Cur_fid - 0x2;
|
||||
Cur_feq = Cur_fid * fid_multiplier + 800;
|
||||
if (Pstate_vid[Pstate_num - 1] >= Min_vid) {
|
||||
Pstate_vid[Pstate_num] = Pstate_vid[Pstate_num - 1];
|
||||
Pstate_volt[Pstate_num] = Pstate_volt[Pstate_num - 1];
|
||||
Pstate_power[Pstate_num] = Pstate_power[Pstate_num - 1];
|
||||
} else {
|
||||
Pstate_vid[Pstate_num] =
|
||||
Pstate_vid[Pstate_num - 1] + PstateStep_coef;
|
||||
Pstate_volt[Pstate_num] =
|
||||
1550 - Pstate_vid[Pstate_num] * 25;
|
||||
Pstate_power[Pstate_num] =
|
||||
(unsigned long long)Pstate_power[0] *
|
||||
Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
|
||||
Pstate_volt[Pstate_num] / (Pstate_feq[0] *
|
||||
Pstate_volt[0] *
|
||||
Pstate_volt[0]);
|
||||
}
|
||||
Pstate_num++;
|
||||
}
|
||||
|
||||
/* Constuct P[Min] State */
|
||||
if (Max_fid == 0x2A && Max_vid != 0x0) {
|
||||
Pstate_fid[Pstate_num] = 0x2;
|
||||
Pstate_feq[Pstate_num] =
|
||||
Pstate_fid[Pstate_num] * fid_multiplier + 800;
|
||||
Pstate_vid[Pstate_num] = Min_vid;
|
||||
Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
|
||||
Pstate_power[Pstate_num] =
|
||||
(unsigned long long)Pstate_power[0] *
|
||||
Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
|
||||
Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] *
|
||||
Pstate_volt[0]);
|
||||
Pstate_num++;
|
||||
} else {
|
||||
Pstate_fid[Pstate_num] = Start_fid;
|
||||
Pstate_feq[Pstate_num] =
|
||||
Pstate_fid[Pstate_num] * fid_multiplier + 800;
|
||||
Pstate_vid[Pstate_num] = Min_vid;
|
||||
Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
|
||||
Pstate_power[Pstate_num] =
|
||||
(unsigned long long)Pstate_power[0] *
|
||||
Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
|
||||
Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] *
|
||||
Pstate_volt[0]);
|
||||
Pstate_num++;
|
||||
}
|
||||
|
||||
/* Print Pstate freq,vid,volt,power */
|
||||
|
||||
for (index = 0; index < Pstate_num; index++) {
|
||||
printk_info("Pstate_freq[%d] = %dMHz\t", index,
|
||||
Pstate_feq[index]);
|
||||
printk_info("Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
|
||||
printk_info("Pstate_volt[%d] = %dmv\t", index,
|
||||
Pstate_volt[index]);
|
||||
printk_info("Pstate_power[%d] = %dmw\n", index,
|
||||
Pstate_power[index]);
|
||||
}
|
||||
|
||||
/*
|
||||
* Modify the DSDT Table to put the actural _PSS package
|
||||
* corefeq-->Pstate_feq[index]
|
||||
* power-->Pstate_power[index]
|
||||
* transitionlatency-->0x64
|
||||
* busmasterlatency-->0x7,
|
||||
* control--> 0xE8202800| Pstate_vid[index]<<6 | Pstate_fid[index]
|
||||
* status --> Pstate_vid[index]<<6 | Pstate_fid[index]
|
||||
* Get the _PSS control method Sig.
|
||||
*/
|
||||
|
||||
dsdt_pointer = (u8 *) dsdt;
|
||||
old_dsdt_length = dsdt->length;
|
||||
new_dsdt_length = old_dsdt_length;
|
||||
printk_info("DSDT reconstruction...\n");
|
||||
for (i = 0x20; i < new_dsdt_length; i++)
|
||||
if ((*(dsdt_pointer + i) == '_')
|
||||
&& (*(dsdt_pointer + i + 1) == 'P')
|
||||
&& (*(dsdt_pointer + i + 2) == 'S')
|
||||
&& (*(dsdt_pointer + i + 3) == 'S')) {
|
||||
|
||||
if ((*(dsdt_pointer + i + 4) !=
|
||||
0x12) | (*(dsdt_pointer + i + 5) !=
|
||||
0x4B) | (*(dsdt_pointer + i + 6) !=
|
||||
0x10)) {
|
||||
printk_info
|
||||
("Error:No _PSS package leader byte!\n");
|
||||
} else {
|
||||
new_package_length =
|
||||
0x10B - Defpkglength * (Maxpstate -
|
||||
Pstate_num);
|
||||
/* two Pstates length will larger than 63, so we need not worry about the length */
|
||||
if (new_package_length > 63) {
|
||||
*(dsdt_pointer + i + 5) =
|
||||
0x40 | (new_package_length & 0xf);
|
||||
*(dsdt_pointer + i + 6) =
|
||||
(new_package_length & 0xff0) >> 4;
|
||||
}
|
||||
*(dsdt_pointer + i + 7) = Pstate_num;
|
||||
}
|
||||
|
||||
if ((*(dsdt_pointer + i + 8) !=
|
||||
0x12) | (*(dsdt_pointer + i + 9) !=
|
||||
0x20) | (*(dsdt_pointer + i + 10) != 0x6))
|
||||
printk_info
|
||||
("Error:No package leader for the first Pstate!\n");
|
||||
for (index = 0; index < Pstate_num; index++) {
|
||||
corefeq = Pstate_feq[index];
|
||||
power = Pstate_power[index];
|
||||
transitionlatency = 0x64;
|
||||
busmasterlatency = 0x7;
|
||||
control =
|
||||
(0x3 << 30) | /* IRT */
|
||||
(0x2 << 28) | /* RVO */
|
||||
(0x1 << 27) | /* ExtType */
|
||||
(0x2 << 20) | /* PLL_LOCK_TIME */
|
||||
(0x0 << 18) | /* MVS */
|
||||
(0x5 << 11) | /* VST */
|
||||
(Pstate_vid[index] << 6) |
|
||||
Pstate_fid[index];
|
||||
status =
|
||||
(Pstate_vid[index] << 6) |
|
||||
Pstate_fid[index];
|
||||
for (byte_index = 0; byte_index < 4;
|
||||
byte_index++) {
|
||||
*(dsdt_pointer + i + 0xC +
|
||||
Defpkglength * index + byte_index) =
|
||||
corefeq >> (8 * byte_index);
|
||||
*(dsdt_pointer + i + 0xC +
|
||||
Defpkglength * index + 0x5 +
|
||||
byte_index) =
|
||||
power >> (8 * byte_index);
|
||||
*(dsdt_pointer + i + 0xC +
|
||||
Defpkglength * index + 0x5 * 2 +
|
||||
byte_index) =
|
||||
transitionlatency >> (8 * byte_index);
|
||||
*(dsdt_pointer + i + 0xC +
|
||||
Defpkglength * index + 0x5 * 3 +
|
||||
byte_index) =
|
||||
busmasterlatency >> (8 * byte_index);
|
||||
*(dsdt_pointer + i + 0xC +
|
||||
Defpkglength * index + 0x5 * 4 +
|
||||
byte_index) =
|
||||
control >> (8 * byte_index);
|
||||
*(dsdt_pointer + i + 0xC +
|
||||
Defpkglength * index + 0x5 * 5 +
|
||||
byte_index) =
|
||||
status >> (8 * byte_index);
|
||||
}
|
||||
}
|
||||
pointer1 =
|
||||
dsdt_pointer + i + 8 + Pstate_num * Defpkglength;
|
||||
pointer2 =
|
||||
dsdt_pointer + i + 8 + Maxpstate * Defpkglength;
|
||||
while (pointer2 < dsdt_pointer + new_dsdt_length) {
|
||||
*pointer1 = *pointer2;
|
||||
pointer1++;
|
||||
pointer2++;
|
||||
}
|
||||
/* Recalcute the DSDT length */
|
||||
new_dsdt_length =
|
||||
new_dsdt_length - Defpkglength * (Maxpstate -
|
||||
Pstate_num);
|
||||
|
||||
/* Search the first processor(CPUx) item and recalculate the processor length */
|
||||
for (j = 0; (dsdt_pointer + i - j) > dsdt_pointer; j++) {
|
||||
if ((*(dsdt_pointer + i - j) == 'C')
|
||||
&& (*(dsdt_pointer + i - j + 1) == 'P')
|
||||
&& (*(dsdt_pointer + i - j + 2) == 'U')) {
|
||||
processor_length =
|
||||
((*(dsdt_pointer + i - j - 1) << 4)
|
||||
| (*(dsdt_pointer + i - j - 2) &
|
||||
0xf));
|
||||
processor_length =
|
||||
processor_length -
|
||||
Defpkglength * (Maxpstate -
|
||||
Pstate_num);
|
||||
*(dsdt_pointer + i - j - 2) =
|
||||
(processor_length & 0xf) | 0x40;
|
||||
*(dsdt_pointer + i - j - 1) =
|
||||
(processor_length & 0xff0) >> 4;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Search the first scope(_PR_) item and recalculate the scope length */
|
||||
for (j = 0; (dsdt_pointer + i - j) > dsdt_pointer; j++) {
|
||||
if ((*(dsdt_pointer + i - j) == '_')
|
||||
&& (*(dsdt_pointer + i - j + 1) == 'P')
|
||||
&& (*(dsdt_pointer + i - j + 2) == 'R')
|
||||
&& (*(dsdt_pointer + i - j + 3) == '_')) {
|
||||
scope_length =
|
||||
((*(dsdt_pointer + i - j - 1) << 4)
|
||||
| (*(dsdt_pointer + i - j - 2) &
|
||||
0xf));
|
||||
scope_length =
|
||||
scope_length -
|
||||
Defpkglength * (Maxpstate -
|
||||
Pstate_num);
|
||||
*(dsdt_pointer + i - j - 2) =
|
||||
(scope_length & 0xf) | 0x40;
|
||||
*(dsdt_pointer + i - j - 1) =
|
||||
(scope_length & 0xff0) >> 4;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Recalculate the DSDT length and fill back to the table */
|
||||
*(dsdt_pointer + 0x4) = new_dsdt_length;
|
||||
*(dsdt_pointer + 0x5) = new_dsdt_length >> 8;
|
||||
|
||||
/*
|
||||
* Recalculate the DSDT checksum and fill back to the table
|
||||
* We must make sure the sum of the whole table is 0
|
||||
*/
|
||||
sum = 0;
|
||||
for (i = 0; i < new_dsdt_length; i++)
|
||||
if (i != 9)
|
||||
sum = sum + *(dsdt_pointer + i);
|
||||
checksum = 0x100 - sum;
|
||||
*(dsdt_pointer + 0x9) = checksum;
|
||||
|
||||
/*Check the DSDT Table */
|
||||
/*
|
||||
* printk_info("The new DSDT table length is %x\n", new_dsdt_length);
|
||||
* printk_info("Details is as below:\n");
|
||||
* for(i=0; i< new_dsdt_length; i++){
|
||||
* printk_info("%x\t",(unsigned char)*(dsdt_pointer+i));
|
||||
* if( ((i+1)&0x7) == 0x0)
|
||||
* printk_info("**0x%x**\n",i-7);
|
||||
*}
|
||||
*/
|
||||
|
||||
return 1;
|
||||
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) {
|
||||
k8acpi_write_vars();
|
||||
amd_model_fxx_generate_powernow(pm_base + 8, 6, 1);
|
||||
return (unsigned long) (acpigen_get_current());
|
||||
}
|
||||
|
||||
|
|
@ -717,10 +253,6 @@ unsigned long write_acpi_tables(unsigned long start)
|
|||
dsdt = (acpi_header_t *) current;
|
||||
memcpy((void *)dsdt, (void *)AmlCode,
|
||||
((acpi_header_t *) AmlCode)->length);
|
||||
if (!pstates_algorithm(dsdt))
|
||||
printk_debug("pstates_algorithm error!\n");
|
||||
else
|
||||
printk_debug("pstates_algorithm success.\n");
|
||||
|
||||
current += dsdt->length;
|
||||
printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length);
|
||||
|
|
|
|||
Loading…
Reference in New Issue