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skylake: PCR: Add Port ID for SCS 

Add the PCR Port ID for the storage controllers and
reformat to put the PCR PIDs in increasing order.

BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: I0f0144ef79d3691fa120dafc9a31d2a681bf2a28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 208242f58759899f17e52593ed6e1dd631334ac9
Original-Change-Id: I942bcf01b0576136c0039aa62f38fe7f3454ba8a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295905
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11532
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2015-08-27 16:35:06 -07:00 committed by Patrick Georgi
parent bf9df75eac
commit fe85ae3f41
1 changed files with 3 additions and 2 deletions
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5
src/soc/intel/skylake/include/soc/pcr.h
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@ -78,9 +78,10 @@
#define PID_GPIOCOM2 0xAD #define PID_GPIOCOM2 0xAD
#define PID_GPIOCOM1 0xAE #define PID_GPIOCOM1 0xAE
#define PID_GPIOCOM0 0xAF #define PID_GPIOCOM0 0xAF
#define PID_LPC 0xC7 #define PID_SCS 0xC0
#define PID_ITSS 0xC4
#define PID_RTC 0xC3 #define PID_RTC 0xC3
#define PID_ITSS 0xC4
#define PID_LPC 0xC7
#define PID_SERIALIO 0xCB #define PID_SERIALIO 0xCB
#define PID_DMI 0xEF #define PID_DMI 0xEF