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mb/google/nissa: Configure the external V1p05/Vnn/VnnSx rails for Nereid 

This patch configures external V1p05/Vnn/VnnSx rails for Nereid
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
  S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide

BUG=b:223102016
TEST=Verified all the UPD values are updated with these configs.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I1df4ea10798354f41fe9cce0f8c478930517207c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This commit is contained in:
V Sowmya 2022-05-17 14:14:39 +05:30 committed by Felix Held
parent 1e44a5b0c7
commit fe97ad37fc
1 changed files with 15 additions and 0 deletions
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15
src/mainboard/google/brya/variants/nereid/overridetree.cb
View File

@ -19,6 +19,21 @@ chip soc/intel/alderlake
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
# Configure external V1P05/Vnn/VnnSx Rails
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
.v1p05_voltage_mv = 1050,
.vnn_voltage_mv = 780,
.vnn_sx_voltage_mv = 1050,
.v1p05_icc_max_ma = 500,
.vnn_icc_max_ma = 500,
}"
device domain 0 on device domain 0 on
device ref i2c1 on device ref i2c1 on
chip drivers/i2c/hid chip drivers/i2c/hid