X60: add dock code for Ultrabase X6
Move the old docking code from romstage.c to dock.c, and use that code both in romstage and SMM code. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Sven Schnelle
parent
1aba096789
commit
fea6bd1690
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@ -17,4 +17,5 @@
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c dock.c
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romstage-y += dock.c
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Binary file not shown.
Binary file not shown.
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@ -0,0 +1,55 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include "smi.h"
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OperationRegion (DLPC, SystemIO, 0x164c, 1)
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Field(DLPC, ByteAcc, NoLock, Preserve)
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{
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, 3,
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DSTA, 1,
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}
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Device(DOCK)
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{
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Name(_HID, "ACPI0003")
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Name(_UID, 0x00)
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Name(_PCL, Package() { \_SB } )
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Method(_DCK, 1, NotSerialized)
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{
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if (Arg0) {
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Sleep(250)
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/* connect dock */
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TRAP(SMI_DOCK_CONNECT)
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} else {
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/* disconnect dock */
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TRAP(SMI_DOCK_DISCONNECT)
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}
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Xor(Arg0, DSTA, Local0)
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Return (Local0)
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}
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Method(_STA, 0, NotSerialized)
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{
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Return (DSTA)
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}
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}
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@ -19,6 +19,7 @@
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* MA 02110-1301 USA
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*/
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#include "smi.h"
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Device(EC)
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{
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Name (_HID, EISAID("PNP0C09"))
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@ -83,6 +84,11 @@ Device(EC)
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\DSPC.BRTD()
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}
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Method(_Q18, 0, NotSerialized)
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{
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Notify(\_SB.PCI0.LPCB.EC.DOCK, 3)
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}
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/* AC status change: present */
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Method(_Q26, 0, NotSerialized)
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{
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@ -111,4 +117,5 @@ Device(EC)
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#include "sleepbutton.asl"
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#include "lid.asl"
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#include "beep.asl"
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#include "dock.asl"
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}
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@ -1,3 +1,4 @@
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#include "smi.h"
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Scope (\_GPE)
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{
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Method(_L18, 0, NotSerialized)
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@ -5,4 +6,16 @@ Scope (\_GPE)
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/* Read EC register to clear wake status */
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Store(\_SB.PCI0.LPCB.EC.WAKE, Local0)
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}
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/* SLICE_ON_3M GPE (Dock status) */
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Method(_L1D, 0, NotSerialized)
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{
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if (GP13) {
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Or(GIV1, 0x20, GIV1)
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Notify(\_SB.PCI0.LPCB.EC.DOCK, 3)
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} else {
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And(GIV1, 0xdf, GIV1)
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Notify(\_SB.PCI0.LPCB.EC.DOCK, 0)
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}
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}
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}
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@ -0,0 +1,249 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <arch/io.h>
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#include <boot/tables.h>
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#include <delay.h>
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#include <arch/io.h>
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#include "dock.h"
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#include "southbridge/intel/i82801gx/i82801gx.h"
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#include "superio/nsc/pc87392/pc87392.h"
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static void dlpc_write_register(int reg, int value)
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{
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outb(reg, 0x164e);
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outb(value, 0x164f);
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}
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static u8 dlpc_read_register(int reg)
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{
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outb(reg, 0x164e);
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return inb(0x164f);
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}
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static void dock_write_register(int reg, int value)
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{
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outb(reg, 0x2e);
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outb(value, 0x2f);
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}
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static u8 dock_read_register(int reg)
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{
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outb(reg, 0x2e);
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return inb(0x2f);
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}
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static void dlpc_gpio_set_mode(int port, int mode)
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{
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dlpc_write_register(0xf0, port);
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dlpc_write_register(0xf1, mode);
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}
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static void dock_gpio_set_mode(int port, int mode, int irq)
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{
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dock_write_register(0xf0, port);
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dock_write_register(0xf1, mode);
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dock_write_register(0xf2, irq);
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}
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static void dlpc_gpio_init(void)
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{
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/* Select GPIO module */
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dlpc_write_register(0x07, 0x07);
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/* GPIO Base Address 0x1680 */
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dlpc_write_register(0x60, 0x16);
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dlpc_write_register(0x61, 0x80);
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/* Activate GPIO */
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dlpc_write_register(0x30, 0x01);
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dlpc_gpio_set_mode(0x00, 3);
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dlpc_gpio_set_mode(0x01, 3);
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dlpc_gpio_set_mode(0x02, 0);
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dlpc_gpio_set_mode(0x03, 3);
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dlpc_gpio_set_mode(0x04, 4);
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dlpc_gpio_set_mode(0x20, 4);
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dlpc_gpio_set_mode(0x21, 4);
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dlpc_gpio_set_mode(0x23, 4);
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}
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int dlpc_init(void)
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{
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int timeout = 1000;
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/* Enable 14.318MHz CLK on CLKIN */
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dlpc_write_register(0x29, 0xa0);
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while(!(dlpc_read_register(0x29) & 0x10) && timeout--)
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udelay(1000);
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if (!timeout)
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return 1;
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/* Select DLPC module */
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dlpc_write_register(0x07, 0x19);
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/* DLPC Base Address 0x164c */
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dlpc_write_register(0x60, 0x16);
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dlpc_write_register(0x61, 0x4c);
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/* Activate DLPC */
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dlpc_write_register(0x30, 0x01);
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outb(0x07, 0x164c);
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timeout = 1000;
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while(!(inb(0x164c) & 8) && timeout--)
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udelay(1000);
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if (!timeout) {
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/* docking failed, disable DLPC switch */
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outb(0x00, 0x164c);
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dlpc_write_register(0x30, 0x00);
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return 1;
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}
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dlpc_gpio_init();
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return 0;
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}
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int dock_connect(void)
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{
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int timeout = 1000;
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/* Assert D_PLTRST# */
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outb(0xfe, 0x1680);
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udelay(1000);
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/* Deassert D_PLTRST# */
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outb(0xff, 0x1680);
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/* startup 14.318MHz Clock */
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dock_write_register(0x29, 0x06);
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/* wait until clock is settled */
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while(!(dock_read_register(0x29) & 0x08) && timeout--)
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udelay(1000);
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if (!timeout)
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return 1;
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/* Pin 6: CLKRUN
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* Pin 72: #DR1
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* Pin 19: #SMI
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* Pin 73: #MTR
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*/
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dock_write_register(0x24, 0x37);
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/* PNF active HIGH */
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dock_write_register(0x25, 0xa0);
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/* disable FDC */
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dock_write_register(0x26, 0x01);
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/* Enable GPIO IRQ to #SMI */
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dock_write_register(0x28, 0x02);
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/* select GPIO */
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dock_write_register(0x07, 0x07);
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/* set base address */
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dock_write_register(0x60, 0x16);
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dock_write_register(0x61, 0x20);
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/* init GPIO pins */
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dock_gpio_set_mode(0x00, PC87392_GPIO_PIN_DEBOUNCE |
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PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x01, PC87392_GPIO_PIN_DEBOUNCE |
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PC87392_GPIO_PIN_PULLUP,
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PC87392_GPIO_PIN_TRIGGERS_SMI);
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dock_gpio_set_mode(0x02, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x03, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x04, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x05, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x06, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x07, PC87392_GPIO_PIN_PULLUP, 0x02);
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dock_gpio_set_mode(0x10, PC87392_GPIO_PIN_DEBOUNCE |
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PC87392_GPIO_PIN_PULLUP,
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PC87392_GPIO_PIN_TRIGGERS_SMI);
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dock_gpio_set_mode(0x11, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x12, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x13, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP |
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PC87392_GPIO_PIN_OE , 0x00);
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dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x20, PC87392_GPIO_PIN_TYPE_PUSH_PULL |
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PC87392_GPIO_PIN_OE, 0x00);
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dock_gpio_set_mode(0x21, PC87392_GPIO_PIN_TYPE_PUSH_PULL |
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PC87392_GPIO_PIN_OE, 0x00);
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dock_gpio_set_mode(0x22, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x23, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x24, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x25, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x26, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x27, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x30, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x31, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x32, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x33, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x34, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x35, PC87392_GPIO_PIN_PULLUP |
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PC87392_GPIO_PIN_OE, 0x00);
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dock_gpio_set_mode(0x36, PC87392_GPIO_PIN_PULLUP, 0x00);
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dock_gpio_set_mode(0x37, PC87392_GPIO_PIN_PULLUP, 0x00);
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/* enable GPIO */
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dock_write_register(0x30, 0x01);
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outb(0x00, 0x1628);
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outb(0x00, 0x1623);
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outb(0x82, 0x1622);
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outb(0xff, 0x1624);
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/* Enable USB and Ultrabay power */
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outb(0x03, 0x1628);
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return 0;
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}
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void dock_disconnect(void)
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{
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/* disconnect LPC bus */
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outb(0x00, 0x164c);
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/* Assert PLTRST and DLPCPD */
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outb(0xfc, 0x1680);
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}
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int dock_present(void)
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{
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return !((inb(DEFAULT_GPIOBASE + 0x0c) >> 13) & 1);
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}
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@ -0,0 +1,8 @@
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#ifndef THINKPAD_X60_DOCK_H
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#define THINKPAD_X60_DOCK_H
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extern int dock_connect(void);
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extern void dock_disconnect(void);
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extern int dock_present(void);
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extern int dlpc_init(void);
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#endif
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@ -24,30 +24,55 @@
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include "southbridge/intel/i82801gx/nvs.h"
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#include <ec/acpi/ec.h>
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#include "dock.h"
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#include "smi.h"
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/* The southbridge SMI handler checks whether gnvs has a
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* valid pointer before calling the trap handler
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*/
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extern global_nvs_t *gnvs;
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static void mainboard_smm_init(void)
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{
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printk(BIOS_DEBUG, "initializing SMI\n");
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/* Enable 0x1600/0x1600 register pair */
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ec_set_bit(0x00, 0x05);
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ec_set_ports(0x1604, 0x1600);
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}
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int mainboard_io_trap_handler(int smif)
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{
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static int smm_initialized;
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if (!smm_initialized) {
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mainboard_smm_init();
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smm_initialized = 1;
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}
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switch (smif) {
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case 0x99:
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printk(BIOS_DEBUG, "Sample\n");
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//gnvs->smif = 0;
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case SMI_DOCK_CONNECT:
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dlpc_init();
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if (!dock_connect()) {
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/* set dock LED to indicate status */
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ec_write(0x0c, 0x88);
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} else {
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/* blink dock LED to indicate failure */
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ec_write(0x0c, 0xc8);
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}
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break;
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case SMI_DOCK_DISCONNECT:
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dock_disconnect();
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ec_write(0x0c, 0x08);
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break;
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default:
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return 0;
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return 1;
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}
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/* On success, the IO Trap Handler returns 0
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* On failure, the IO Trap Handler returns a value != 0
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*
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* For now, we force the return value to 0 and log all traps to
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* see what's going on.
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*/
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//gnvs->smif = 0;
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return 1;
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* On failure, the IO Trap Handler returns a value != 0 */
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return 0;
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}
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|
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@ -37,6 +37,7 @@
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#include "northbridge/intel/i945/i945.h"
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#include "northbridge/intel/i945/raminit.h"
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#include "southbridge/intel/i82801gx/i82801gx.h"
|
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#include "dock.h"
|
||||
|
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void setup_ich7_gpios(void)
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{
|
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|
|
@ -107,78 +108,6 @@ static void pnp_write_register(device_t dev, int reg, int val)
|
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outb(val, port+1);
|
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}
|
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|
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static void dock_write_register(int reg, int value)
|
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{
|
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outb(reg, 0x164e);
|
||||
outb(value, 0x164f);
|
||||
/* original software reads the chip id after every
|
||||
I/O operation. Not sure if they are doing it for
|
||||
some code switching depending on hardware or just
|
||||
to have a delay after every operation.
|
||||
|
||||
Do it the same way for now, we may remove it later
|
||||
if it isn't needed
|
||||
*/
|
||||
outb(0x20, 0x164e);
|
||||
inb(0x164f);
|
||||
}
|
||||
|
||||
static void dock_dlpc_init(void)
|
||||
{
|
||||
/* Select DLPC module */
|
||||
dock_write_register(0x07, 0x19);
|
||||
/* DLPC Base Address 0x164c */
|
||||
dock_write_register(0x60, 0x16);
|
||||
dock_write_register(0x61, 0x4c);
|
||||
/* Activate DLPC */
|
||||
dock_write_register(0x30, 0x01);
|
||||
outb(0x07, 0x164c);
|
||||
|
||||
while(!(inb(0x164c) & 8))
|
||||
udelay(100 * 100);
|
||||
}
|
||||
|
||||
static void dock_gpio_set_mode(int port, int mode)
|
||||
{
|
||||
dock_write_register(0xf0, port);
|
||||
dock_write_register(0xf1, mode);
|
||||
|
||||
}
|
||||
|
||||
static void dock_gpio_init(void)
|
||||
{
|
||||
/* Select GPIO module */
|
||||
dock_write_register(0x07, 0x07);
|
||||
/* GPIO Base Address 0x1680 */
|
||||
dock_write_register(0x60, 0x16);
|
||||
dock_write_register(0x61, 0x80);
|
||||
|
||||
/* Activate GPIO */
|
||||
dock_write_register(0x30, 0x01);
|
||||
|
||||
dock_gpio_set_mode(0x00, 3);
|
||||
dock_gpio_set_mode(0x01, 3);
|
||||
dock_gpio_set_mode(0x02, 0);
|
||||
dock_gpio_set_mode(0x03, 3);
|
||||
dock_gpio_set_mode(0x04, 4);
|
||||
dock_gpio_set_mode(0x20, 4);
|
||||
dock_gpio_set_mode(0x21, 4);
|
||||
dock_gpio_set_mode(0x23, 4);
|
||||
}
|
||||
|
||||
static void connect_dock(void)
|
||||
{
|
||||
/* Enable 14.318MHz CLK on CLKIN */
|
||||
dock_write_register(0x29, 0x00);
|
||||
dock_write_register(0x29, 0xa0);
|
||||
dock_gpio_init();
|
||||
/* Assert D_PLTRST# */
|
||||
outb(0xfe, 0x1680);
|
||||
dock_dlpc_init();
|
||||
/* Deassert D_PLTRST# */
|
||||
outb(0xff, 0x1680);
|
||||
}
|
||||
|
||||
static void early_superio_config(void)
|
||||
{
|
||||
device_t dev;
|
||||
|
|
@ -306,12 +235,17 @@ void main(unsigned long bist)
|
|||
|
||||
ich7_enable_lpc();
|
||||
|
||||
connect_dock();
|
||||
|
||||
early_superio_config();
|
||||
|
||||
/* Set up the console */
|
||||
uart_init();
|
||||
/* dock_init initializes the DLPC switch on
|
||||
* thinpad side, so this is required even
|
||||
* if we're undocked.
|
||||
*/
|
||||
if (!dlpc_init() && dock_present()) {
|
||||
dock_connect();
|
||||
early_superio_config();
|
||||
/* Set up the console */
|
||||
uart_init();
|
||||
}
|
||||
|
||||
#if CONFIG_USBDEBUG
|
||||
i82801gx_enable_usbdebug(1);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
#ifndef MAINBOARD_LENOVO_X60_SMI_H
|
||||
#define MAINBOARD_LENOVO_X60_SMI_H
|
||||
|
||||
#define SMI_DOCK_CONNECT 0x01
|
||||
#define SMI_DOCK_DISCONNECT 0x02
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue