soc/intel/apollolake: Switch to snake case for DisableComplianceMode

For a unification of the naming convension, change from pascal case to
snake case style for parameter 'DisableComplianceMode'.

Change-Id: I9d5605134a753f161a66857c7f78844ae7490cd6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>

src/mainboard/google/octopus/variants/bloog/overridetree.cb

@@ -168,5 +168,5 @@ chip soc/intel/apollolake
 	end
 
 	# Disable compliance mode
-	register "DisableComplianceMode" = "1"
+	register "disable_compliance_mode" = "1"
 end

src/mainboard/google/octopus/variants/bobba/overridetree.cb

@@ -227,6 +227,6 @@ chip soc/intel/apollolake
 	end
 
 	# Disable compliance mode
-	register "DisableComplianceMode" = "1"
+	register "disable_compliance_mode" = "1"
 	register "disable_xhci_lfps_pm" = "0"
 end

src/mainboard/google/octopus/variants/casta/overridetree.cb

@@ -150,5 +150,5 @@ chip soc/intel/apollolake
 	end
 
 	# Disable compliance mode
-	register "DisableComplianceMode" = "1"
+	register "disable_compliance_mode" = "1"
 end

src/mainboard/google/octopus/variants/dood/overridetree.cb

@@ -162,6 +162,6 @@ chip soc/intel/apollolake
 	end
 
 	# Disable compliance mode
-	register "DisableComplianceMode" = "1"
+	register "disable_compliance_mode" = "1"
 	register "disable_xhci_lfps_pm" = "0"
 end

src/mainboard/google/octopus/variants/fleex/overridetree.cb

@@ -85,7 +85,7 @@ chip soc/intel/apollolake
 	}"
 
 	# Disable compliance mode
-	register "DisableComplianceMode" = "1"
+	register "disable_compliance_mode" = "1"
 	register "disable_xhci_lfps_pm" = "0"
 
 	device domain 0 on

src/mainboard/google/octopus/variants/foob/overridetree.cb

@@ -163,5 +163,5 @@ chip soc/intel/apollolake
 	end
 
 	# Disable xHCI compliance mode
-	register "DisableComplianceMode" = "1"
+	register "disable_compliance_mode" = "1"
 end

src/mainboard/google/octopus/variants/garg/overridetree.cb

@@ -204,6 +204,6 @@ chip soc/intel/apollolake
 	end
 
 	# Disable compliance mode
-	register "DisableComplianceMode" = "1"
+	register "disable_compliance_mode" = "1"
 	register "disable_xhci_lfps_pm" = "0"
 end

src/mainboard/google/octopus/variants/lick/overridetree.cb

@@ -116,5 +116,5 @@ chip soc/intel/apollolake
 
 	# Disable compliance mode
 
-	register "DisableComplianceMode" = "1"
+	register "disable_compliance_mode" = "1"
 end

src/mainboard/google/octopus/variants/meep/overridetree.cb

@@ -248,5 +248,5 @@ chip soc/intel/apollolake
 	end
 
 	# Disable compliance mode
-	register "DisableComplianceMode" = "1"
+	register "disable_compliance_mode" = "1"
 end

src/mainboard/google/octopus/variants/phaser/overridetree.cb

@@ -202,5 +202,5 @@ chip soc/intel/apollolake
 	end
 
 	# Disable xHCI compliance mode
-	register "DisableComplianceMode" = "1"
+	register "disable_compliance_mode" = "1"
 end

src/mainboard/starlabs/lite/variants/glk/devicetree.cb

@@ -31,7 +31,7 @@ chip soc/intel/apollolake
 	register "prt0_gpio"			= "GPIO_PRT0_UDEF"
 
 	register "usb_config_override"		= "1"
-	register "DisableComplianceMode"	= "1"
+	register "disable_compliance_mode"	= "1"
 
 	register "pcie_rp_clkreq_pin[0]"	= "CLKREQ_DISABLED"
 	register "pcie_rp_clkreq_pin[1]"	= "CLKREQ_DISABLED"

src/mainboard/starlabs/lite/variants/glkr/devicetree.cb

@@ -31,7 +31,7 @@ chip soc/intel/apollolake
 	register "prt0_gpio"			= "GPIO_PRT0_UDEF"
 
 	register "usb_config_override"		= "1"
-	register "DisableComplianceMode"	= "1"
+	register "disable_compliance_mode"	= "1"
 
 	register "pcie_rp_clkreq_pin[0]"	= "CLKREQ_DISABLED"
 	register "pcie_rp_clkreq_pin[1]"	= "CLKREQ_DISABLED"

src/soc/intel/apollolake/chip.c

@@ -607,7 +607,7 @@ static void glk_fsp_silicon_init_params_cb(
 	/*
 	 * Options to disable XHCI Link Compliance Mode.
 	 */
-	silconfig->DisableComplianceMode = cfg->DisableComplianceMode;
+	silconfig->DisableComplianceMode = cfg->disable_compliance_mode;
 
 	/*
 	 * Options to change USB3 ModPhy setting for Integrated Filter value.

src/soc/intel/apollolake/chip.h

@@ -184,7 +184,7 @@ struct soc_intel_apollolake_config {
 	 * disable Compliance Mode. Set TRUE to disable Compliance Mode.
 	 * 0:FALSE(Default), 1:True.
 	 */
-	uint8_t DisableComplianceMode;
+	uint8_t disable_compliance_mode;
 
 	/* Options to change USB3 ModPhy setting for the Integrated Filter (IF)
 	 * value. Default is 0 to not changing default IF value (0x12). Set