mainboard/reef: add variant support to ASL code
There are certain board-specific options for reef variants. The big one is the DPTF settings. Rearrange the ASL files such that dsdt.asl is the main landing area. The ACPI options for Chrome EC are contained in the variant/ec.h header so the actual code #includes can just reside in dstd.asl. Since most of the mainboard specific peripherals are auto generated by the acpigen from devicetree there's no real separate need for mainboard.asl. The one thing not addressed in this CL is the notion of a variant having the Chrome EC or not (along with lid, etc). Future indirection can be provided when needed to address that requirement. BUG=chrome-os-partner:56677 Change-Id: I5c888f5fc64913dcff010c28f87e69ac5449e6b6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16604 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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@ -1,23 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Enable EC backed ALS device in ACPI */
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#define EC_ENABLE_ALS_DEVICE
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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@ -1,42 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <variant/ec.h>
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#include <variant/gpio.h>
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Scope (\_SB)
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{
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Device (LID0)
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{
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Name (_HID, EisaId ("PNP0C0D"))
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Method (_LID, 0)
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{
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Return (\_SB.PCI0.LPCB.EC0.LIDS)
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}
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Name (_PRW, Package () { GPE_EC_WAKE, 0x3 })
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}
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Device (PWRB)
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{
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Name (_HID, EisaId ("PNP0C0C"))
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}
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}
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Scope (\_SB.PCI0.LPCB)
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{
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/* Chrome OS Embedded Controller */
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#include "superio.asl"
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#include "ec.asl"
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}
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@ -13,6 +13,9 @@
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* GNU General Public License for more details.
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*/
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#include <variant/ec.h>
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#include <variant/gpio.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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@ -43,11 +46,42 @@ DefinitionBlock(
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/* Chipset specific sleep states */
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#include <soc/intel/apollolake/acpi/sleepstates.asl>
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/* Mainboard Specific devices */
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#include "acpi/mainboard.asl"
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/* LID and Power button. */
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Scope (\_SB)
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{
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Device (LID0)
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{
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Name (_HID, EisaId ("PNP0C0D"))
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Method (_LID, 0)
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{
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Return (\_SB.PCI0.LPCB.EC0.LIDS)
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}
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Name (_PRW, Package () { GPE_EC_WAKE, 0x3 })
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}
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Device (PWRB)
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{
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Name (_HID, EisaId ("PNP0C0C"))
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}
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}
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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Scope (\_SB) {
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/* Dynamic Platform Thermal Framework */
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#include "acpi/dptf.asl"
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Scope (\_SB)
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{
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/* Per board variant specific definitions. */
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#include <variant/acpi/dptf.asl>
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/* Include soc specific DPTF changes */
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#include <soc/intel/apollolake/acpi/dptf.asl>
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/* Include common dptf ASL files */
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#include <soc/intel/common/acpi/dptf/dptf.asl>
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}
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}
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@ -87,8 +87,3 @@ Name (MPPC, Package ()
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1000 /* StepSize */
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}
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})
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/* Include soc specific DPTF changes */
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#include <soc/intel/apollolake/acpi/dptf.asl>
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/* Include common dptf ASL files */
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#include <soc/intel/common/acpi/dptf/dptf.asl>
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
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/*
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* ACPI related definitions for ASL code.
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*/
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/* Enable EC backed ALS device in ACPI */
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#define EC_ENABLE_ALS_DEVICE
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
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#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
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#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
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#endif
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* GNU General Public License for more details.
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*/
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#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
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#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
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#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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#include <baseboard/acpi/dptf.asl>
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