vendorcode/amd/agesa: Tidy up gcccar.inc
Change register preservations and fix comments about register usage accordingly. Do this to avoid use of %mm0-2 registers inside macros defined in gcccar.inc, as future implementation of C_BOOTBLOCK_ENVIRONMENT will use them as well. Adjust caller side accordingly. Change-Id: Ic76fcc31ae714baf5259d17c41b62a3610aa947b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This commit is contained in:
parent
5a0d29d460
commit
fec6fa799c
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@ -32,7 +32,7 @@
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cache_as_ram_setup:
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/* Preserve BIST. */
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movl %eax, %ebp
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movd %eax, %mm0
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post_code(0xa0)
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@ -45,7 +45,6 @@ cache_as_ram_setup:
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post_code(0xa1)
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/* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */
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AMD_ENABLE_STACK
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/* Align the stack. */
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@ -96,19 +95,18 @@ cache_as_ram_setup:
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#endif
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/* Calling conventions preserve BIST in %ebp. */
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call early_all_cores
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/* Must maintain 16-byte stack alignment here. */
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pushl $0x0
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pushl $0x0
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pushl $0x0
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pushl %ebp
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movd %mm0, %eax /* bist */
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pushl %eax
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call romstage_main
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movl %eax, %ebx
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movl %eax, %esp
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/* Register %ebx is new stacktop for remaining of romstage.
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/* Register %esp is new stacktop for remaining of romstage.
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* It is the only register preserved in AMD_DISABLE_STACK.
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*/
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@ -125,7 +123,6 @@ disable_cache_as_ram:
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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movl %ebx, %esp
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call romstage_after_car
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/* Should never see this postcode */
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@ -1201,7 +1201,7 @@ node_core_f15_exit:
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* AMD_ENABLE_STACK: Setup a stack
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*
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* In:
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* EBX = Return address (preserved)
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* No inputs
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*
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* Out:
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* SS:ESP - Our new private stack location
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@ -1212,11 +1212,8 @@ node_core_f15_exit:
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*
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* Requirements:
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* * This routine presently is limited to a max of 64 processor cores
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* Preserved:
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* ebx ebp
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* Destroyed:
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* eax, ecx, edx, edi, esi, ds, es, ss, esp
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* mmx0, mmx1
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* EBX, EDX, EDI, ESI, EBP, DS, ES
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*
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* Description:
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* Fixed MTRR address allocation to cores:
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@ -1276,8 +1273,6 @@ node_core_f15_exit:
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# Note that SS:ESP will be default stack. Note that this stack
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# routine will not be used after memory has been initialized. Because
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# of its limited lifetime, it will not conflict with typical PCI devices.
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movd %ebx, %mm0 # Put return address in a safe place
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movd %ebp, %mm1 # Save some other user registers
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# get node id and core id of current executing core
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GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)
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@ -1589,9 +1584,6 @@ ClearTheStack: # Stack base is in SS, stack pointer is
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or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up)
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#.endif
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0:
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movd %mm0, %ebx # Restore return address
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movd %mm1, %ebp
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.endm
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/*****************************************************************************
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@ -1611,17 +1603,15 @@ ClearTheStack: # Stack base is in SS, stack pointer is
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* none
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*
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* Out:
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* EAX = AGESA_SUCCESS
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* none
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*
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* Preserved:
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* ebx
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* ESP
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* Destroyed:
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* eax, ecx, edx, esp
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* EAX, EBX, ECX, EDX, EDI, ESI
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*****************************************************************************/
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.macro AMD_DISABLE_STACK
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mov %ebx, %esp # Save return address
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# get node/core/flags of current executing core
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GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
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@ -1647,7 +1637,4 @@ ClearTheStack: # Stack base is in SS, stack pointer is
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AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations
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mov %esp, %ebx
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xor %eax, %eax
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.endm
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@ -1181,7 +1181,7 @@ node_core_f15_exit:
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* AMD_ENABLE_STACK: Setup a stack
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*
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* In:
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* EBX = Return address (preserved)
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* No inputs
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*
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* Out:
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* SS:ESP - Our new private stack location
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@ -1192,11 +1192,8 @@ node_core_f15_exit:
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*
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* Requirements:
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* * This routine presently is limited to a max of 64 processor cores
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* Preserved:
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* ebx ebp
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* Destroyed:
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* eax, ecx, edx, edi, esi, ds, es, ss, esp
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* mmx0, mmx1
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* EBX, EDX, EDI, ESI, EBP, DS, ES
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*
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* Description:
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* Fixed MTRR address allocation to cores:
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@ -1256,8 +1253,6 @@ node_core_f15_exit:
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# Note that SS:ESP will be default stack. Note that this stack
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# routine will not be used after memory has been initialized. Because
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# of its limited lifetime, it will not conflict with typical PCI devices.
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movd %ebx, %mm0 # Put return address in a safe place
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movd %ebp, %mm1 # Save some other user registers
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# get node id and core id of current executing core
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GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)
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@ -1569,9 +1564,6 @@ ClearTheStack: # Stack base is in SS, stack pointer is
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or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up)
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#.endif
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0:
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movd %mm0, %ebx # Restore return address
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movd %mm1, %ebp
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.endm
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/*****************************************************************************
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@ -1582,17 +1574,15 @@ ClearTheStack: # Stack base is in SS, stack pointer is
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* none
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*
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* Out:
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* EAX = AGESA_SUCCESS
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* none
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*
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* Preserved:
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* ebx
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* ESP
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* Destroyed:
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* eax, ecx, edx, esp
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* EAX, EBX, ECX, EDX, EDI, ESI
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*****************************************************************************/
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.macro AMD_DISABLE_STACK
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mov %ebx, %esp # Save return address
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# get node/core/flags of current executing core
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GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
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@ -1618,7 +1608,4 @@ ClearTheStack: # Stack base is in SS, stack pointer is
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AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations
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mov %esp, %ebx
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xor %eax, %eax
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.endm
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@ -1181,7 +1181,7 @@ node_core_f15_exit:
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* AMD_ENABLE_STACK: Setup a stack
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*
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* In:
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* EBX = Return address (preserved)
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* No inputs
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*
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* Out:
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* SS:ESP - Our new private stack location
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@ -1192,11 +1192,8 @@ node_core_f15_exit:
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*
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* Requirements:
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* * This routine presently is limited to a max of 64 processor cores
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* Preserved:
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* ebx ebp
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* Destroyed:
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* eax, ecx, edx, edi, esi, ds, es, ss, esp
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* mmx0, mmx1
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* EBX, EDX, EDI, ESI, EBP, DS, ES
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*
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* Description:
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* Fixed MTRR address allocation to cores:
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@ -1256,8 +1253,6 @@ node_core_f15_exit:
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# Note that SS:ESP will be default stack. Note that this stack
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# routine will not be used after memory has been initialized. Because
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# of its limited lifetime, it will not conflict with typical PCI devices.
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movd %ebx, %mm0 # Put return address in a safe place
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movd %ebp, %mm1 # Save some other user registers
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# get node id and core id of current executing core
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GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)
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@ -1569,9 +1564,6 @@ ClearTheStack: # Stack base is in SS, stack pointer is
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or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up)
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#.endif
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0:
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movd %mm0, %ebx # Restore return address
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movd %mm1, %ebp
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.endm
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/*****************************************************************************
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@ -1582,17 +1574,15 @@ ClearTheStack: # Stack base is in SS, stack pointer is
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* none
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*
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* Out:
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* EAX = AGESA_SUCCESS
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* none
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*
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* Preserved:
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* ebx
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* ESP
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* Destroyed:
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* eax, ecx, edx, esp
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* EAX, EBX, ECX, EDX, EDI, ESI
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*****************************************************************************/
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.macro AMD_DISABLE_STACK
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mov %ebx, %esp # Save return address
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# get node/core/flags of current executing core
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GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
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@ -1618,7 +1608,4 @@ ClearTheStack: # Stack base is in SS, stack pointer is
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AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations
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mov %esp, %ebx
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xor %eax, %eax
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.endm
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@ -1216,7 +1216,7 @@ node_core_f15_exit:
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* AMD_ENABLE_STACK: Setup a stack
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*
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* In:
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* EBX = Return address (preserved)
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* No inputs
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*
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* Out:
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* SS:ESP - Our new private stack location
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@ -1227,11 +1227,8 @@ node_core_f15_exit:
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*
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* Requirements:
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* * This routine presently is limited to a max of 64 processor cores
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* Preserved:
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* ebx ebp
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* Destroyed:
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* eax, ecx, edx, edi, esi, ds, es, ss, esp
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* mmx0, mmx1
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* EBX, EDX, EDI, ESI, EBP, DS, ES
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*
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* Description:
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* Fixed MTRR address allocation to cores:
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@ -1291,8 +1288,6 @@ node_core_f15_exit:
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# Note that SS:ESP will be default stack. Note that this stack
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# routine will not be used after memory has been initialized. Because
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# of its limited lifetime, it will not conflict with typical PCI devices.
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movd %ebx, %mm0 # Put return address in a safe place
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movd %ebp, %mm1 # Save some other user registers
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# get node id and core id of current executing core
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GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)
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@ -1604,9 +1599,6 @@ ClearTheStack: # Stack base is in SS, stack pointer is
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or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up)
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#.endif
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0:
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movd %mm0, %ebx # Restore return address
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movd %mm1, %ebp
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.endm
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/*****************************************************************************
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@ -1626,17 +1618,15 @@ ClearTheStack: # Stack base is in SS, stack pointer is
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* none
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*
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* Out:
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* EAX = AGESA_SUCCESS
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* none
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*
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* Preserved:
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* ebx
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* ESP
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* Destroyed:
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* eax, ecx, edx, esp
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* EAX, EBX, ECX, EDX, EDI, ESI
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*****************************************************************************/
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.macro AMD_DISABLE_STACK
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mov %ebx, %esp # Save return address
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# get node/core/flags of current executing core
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GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
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@ -1662,7 +1652,4 @@ ClearTheStack: # Stack base is in SS, stack pointer is
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AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations
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mov %esp, %ebx
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xor %eax, %eax
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.endm
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|
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@ -1511,7 +1511,7 @@ node_core_f15_exit:
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* AMD_ENABLE_STACK: Setup a stack
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*
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* In:
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* EBX = Return address (preserved)
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* No inputs
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*
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* Out:
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* SS:ESP - Our new private stack location
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@ -1522,11 +1522,8 @@ node_core_f15_exit:
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*
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* Requirements:
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* * This routine presently is limited to a max of 64 processor cores
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* Preserved:
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* ebx ebp
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* Destroyed:
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* eax, ecx, edx, edi, esi, ds, es, ss, esp
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* mmx0, mmx1
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* EBX, EDX, EDI, ESI, EBP, DS, ES
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*
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* Description:
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* Fixed MTRR address allocation to cores:
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@ -1586,8 +1583,6 @@ node_core_f15_exit:
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# Note that SS:ESP will be default stack. Note that this stack
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# routine will not be used after memory has been initialized. Because
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# of its limited lifetime, it will not conflict with typical PCI devices.
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movd %ebx, %mm0 # Put return address in a safe place
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movd %ebp, %mm1 # Save some other user registers
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# get node id and core id of current executing core
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GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)
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@ -1899,9 +1894,6 @@ ClearTheStack: # Stack base is in SS, stack pointer is
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or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up)
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#.endif
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0:
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movd %mm0, %ebx # Restore return address
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movd %mm1, %ebp
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.endm
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/*****************************************************************************
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@ -1921,17 +1913,15 @@ ClearTheStack: # Stack base is in SS, stack pointer is
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* none
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*
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* Out:
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* EAX = AGESA_SUCCESS
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* none
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*
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* Preserved:
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* ebx
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* ESP
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* Destroyed:
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* eax, ecx, edx, esp
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* EAX, EBX, ECX, EDX, EDI, ESI
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*****************************************************************************/
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.macro AMD_DISABLE_STACK
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mov %ebx, %esp # Save return address
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# get node/core/flags of current executing core
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GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
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@ -1957,7 +1947,4 @@ ClearTheStack: # Stack base is in SS, stack pointer is
|
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|
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AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations
|
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mov %esp, %ebx
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xor %eax, %eax
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.endm
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|
|
|
@ -874,7 +874,7 @@ node_core_f16_exit:
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* AMD_ENABLE_STACK: Setup a stack
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*
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* In:
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* EBX = Return address (preserved)
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* No inputs
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*
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* Out:
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* SS:ESP - Our new private stack location
|
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|
@ -885,11 +885,8 @@ node_core_f16_exit:
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*
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* Requirements:
|
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* * This routine presently is limited to a max of 64 processor cores
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* Preserved:
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* ebx ebp
|
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* Destroyed:
|
||||
* eax, ecx, edx, edi, esi, ds, es, ss, esp
|
||||
* mmx0, mmx1
|
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* EBX, EDX, EDI, ESI, EBP, DS, ES
|
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*
|
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* Description:
|
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* Fixed MTRR address allocation to cores:
|
||||
|
@ -949,8 +946,6 @@ node_core_f16_exit:
|
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# Note that SS:ESP will be default stack. Note that this stack
|
||||
# routine will not be used after memory has been initialized. Because
|
||||
# of its limited lifetime, it will not conflict with typical PCI devices.
|
||||
movd %ebx, %mm0 # Put return address in a safe place
|
||||
movd %ebp, %mm1 # Save some other user registers
|
||||
|
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# get node id and core id of current executing core
|
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GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)
|
||||
|
@ -1262,9 +1257,6 @@ ClearTheStack: # Stack base is in SS, stack pointer is
|
|||
or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up)
|
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#.endif
|
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0:
|
||||
|
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movd %mm0, %ebx # Restore return address
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movd %mm1, %ebp
|
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.endm
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/*****************************************************************************
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@ -1284,17 +1276,15 @@ ClearTheStack: # Stack base is in SS, stack pointer is
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* none
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||||
*
|
||||
* Out:
|
||||
* EAX = AGESA_SUCCESS
|
||||
* none
|
||||
*
|
||||
* Preserved:
|
||||
* ebx
|
||||
* ESP
|
||||
* Destroyed:
|
||||
* eax, ecx, edx, esp
|
||||
* EAX, EBX, ECX, EDX, EDI, ESI
|
||||
*****************************************************************************/
|
||||
.macro AMD_DISABLE_STACK
|
||||
|
||||
mov %ebx, %esp # Save return address
|
||||
|
||||
# get node/core/flags of current executing core
|
||||
GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
|
||||
|
||||
|
@ -1320,7 +1310,4 @@ ClearTheStack: # Stack base is in SS, stack pointer is
|
|||
|
||||
AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations
|
||||
|
||||
mov %esp, %ebx
|
||||
xor %eax, %eax
|
||||
|
||||
.endm
|
||||
|
|
Loading…
Reference in New Issue