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nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h 

Certain registered DIMMs failed training due to an error
likely introduced during historical rebase.  Ensure that
the SubMemclkRegDly bit is set according to BKDG
recommendations on Family 15 processors.

Change-Id: I24c95265dada9eabf4df280b6f2b4a1eb9cecaf1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13148
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2015-11-24 14:11:52 -06:00 committed by Martin Roth
parent 31682364ba
commit fec8872c9d
1 changed files with 3 additions and 0 deletions
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3
src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
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@ -66,6 +66,9 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat,
misc2 |= ((cs_mux_67 & 0x1) << 27);
misc2 &= ~(0x1 << 26); /* CsMux45 = cs_mux_45 */
misc2 |= ((cs_mux_45 & 0x1) << 26);
if (pDCTstat->Status & (1 << SB_Registered))
misc2 |= 1 << SubMemclkRegDly;
} else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) {
if (pDCTstat->Status & (1 << SB_Registered)) {
misc2 |= 1 << SubMemclkRegDly;