sc7180: Fix DDR training failure during warm reset with OTA

Problem: OTA is triggering warmboot, where DDR is
in self-refresh mode. Due to which DDR training
is not going well.

Change: Verify reboot type in case of OTA. If it is warmboot, will
force for cold boot inorder to trigger DDR training

BUG=b:236990316
TEST=Validated on qualcomm sc7180 development board.

Test observation: Cold boot is triggered forcefully,
if current reboot is warmboot in case of OTA

Signed-off-by: Venkat Thogaru <quic_thogaru@quicinc.com>
Change-Id: I908370662292d9f768d1ac89452775178e07fc78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67406
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/trogdor/Makefile.inc

@@ -13,6 +13,9 @@ verstage-y += chromeos.c
 romstage-y += romstage.c
 romstage-y += boardid.c
 romstage-y += chromeos.c
+ifneq ($(CONFIG_BOARD_GOOGLE_BUBS),y)
+romstage-y += reset.c
+endif
 
 ramstage-y += mainboard.c
 ifneq ($(CONFIG_BOARD_GOOGLE_BUBS),y)

src/soc/qualcomm/common/include/soc/qclib_common.h

@@ -44,6 +44,7 @@ struct qclib_cb_if_table_entry {
 
 /* GA_BMASK_VALUES (global_attributes bit mask values) */
 #define QCLIB_GA_ENABLE_UART_LOGGING   0x00000001
+#define QCLIB_GA_FORCE_COLD_REBOOT BIT(3)
 
 #define QCLIB_INTERFACE_VERSION 0x00000001
 #define QCLIB_MAX_NUMBER_OF_ENTRIES 16

src/soc/qualcomm/common/qclib.c

@@ -16,6 +16,7 @@
 #include <security/vboot/misc.h>
 #include <vb2_api.h>
 #include <commonlib/bsd/mem_chip_info.h>
+#include <include/reset.h>
 
 #define QCLIB_VERSION 0
 
@@ -276,6 +277,11 @@ void qclib_load_and_run(void)
 	mmu_restore_context(&pre_qclib_mmu_context);
 	mmu_enable();
 
+	if (qclib_cb_if_table.global_attributes & QCLIB_GA_FORCE_COLD_REBOOT) {
+		printk(BIOS_NOTICE, "QcLib requested cold reboot\n");
+		board_reset();
+	}
+
 	/* step through I/F table, handling return values */
 	for (i = 0; i < qclib_cb_if_table.num_entries; i++)
 		if (qclib_cb_if_table.te[i].blob_attributes &