soc/intel/alderlake: Rename pch_init() code

Rename the pch_init function to bootblock_pch_init to
maintain the parity with previous generation SoC code block.

Refer to commit 1201696.

Change-Id: Id2a89b2f64b58079062d79e07efbdcfad7ed3d2d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45189
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2020-09-09 12:09:43 +05:30
parent 4df75dc498
commit fed1a1a8b0
3 changed files with 3 additions and 3 deletions

View File

@ -25,7 +25,7 @@ void bootblock_soc_early_init(void)
void bootblock_soc_init(void) void bootblock_soc_init(void)
{ {
report_platform_info(); report_platform_info();
pch_init(); bootblock_pch_init();
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
tco_configure(); tco_configure();

View File

@ -138,7 +138,7 @@ void pch_early_iorange_init(void)
pch_enable_lpc(); pch_enable_lpc();
} }
void pch_init(void) void bootblock_pch_init(void)
{ {
/* /*
* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,

View File

@ -8,7 +8,7 @@ void bootblock_cpu_init(void);
void bootblock_pch_early_init(void); void bootblock_pch_early_init(void);
/* Bootblock post console init programming */ /* Bootblock post console init programming */
void pch_init(void); void bootblock_pch_init(void);
void pch_early_iorange_init(void); void pch_early_iorange_init(void);
void report_platform_info(void); void report_platform_info(void);