google/kahlee: Add SPD function

Add the mainboard_spd_read function in romstage and call the variants
function. Grunt is the baseboard and has soldered down memory, so add
it for the default weak SPD functions and build the SPDs in cbfs.
Kahlee overrides the weak SPD function and falls back to the soc
I2C SPD functions.

BUG=b:67845441
TEST=Build and boot Kahlee.

Change-Id: I789002bfadc1a2b24f9046708986d29c0e2daf33
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/mainboard/google/kahlee/Kconfig

@@ -24,6 +24,7 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE
 	select EC_GOOGLE_CHROMEEC_LPC
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_TABLES
+	select GENERIC_SPD_BIN
 	select GFXUMA
 	select GOOGLE_SMBIOS_MAINBOARD_VERSION
 	select MAINBOARD_HAS_CHROMEOS

src/mainboard/google/kahlee/romstage.c

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -12,3 +12,11 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
+
+#include <amdblocks/dimm_spd.h>
+#include <baseboard/variants.h>
+
+int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len)
+{
+	return variant_mainboard_read_spd(spdAddress, buf, len);
+}

src/mainboard/google/kahlee/variants/baseboard/Makefile.inc

@@ -19,4 +19,3 @@ romstage-y += gpio.c
 romstage-y += memory.c
 
 ramstage-y += gpio.c
-ramstage-y += memory.c

src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h

@@ -24,5 +24,6 @@
 const GPIO_CONTROL *get_gpio_table(void);
 const struct sci_source *get_gpe_table(size_t *num);
 uint8_t variant_memory_sku(void);
+int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len);
 
 #endif /* __BASEBOARD_VARIANTS_H__ */

src/mainboard/google/kahlee/variants/baseboard/memory.c

@@ -13,9 +13,12 @@
  * GNU General Public License for more details.
  */
 
-#include <gpio.h> /* src/include/gpio.h */
 #include <baseboard/variants.h>
+#include <console/console.h>
+#include <gpio.h> /* src/include/gpio.h */
+#include <spd_bin.h>
 #include <variant/gpio.h>
+#include <amdblocks/dimm_spd.h>
 
 uint8_t __attribute__((weak)) variant_memory_sku(void)
 {
@@ -28,3 +31,29 @@ uint8_t __attribute__((weak)) variant_memory_sku(void)
 
 	return gpio_base2_value(pads, ARRAY_SIZE(pads));
 }
+
+int __attribute__((weak)) variant_mainboard_read_spd(uint8_t spdAddress,
+							char *buf, size_t len)
+{
+	struct region_device spd_rdev;
+	u8 spd_index = variant_memory_sku();
+
+	printk(BIOS_INFO, "%s SPD index %d\n", __func__, spd_index);
+
+	if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) {
+		printk(BIOS_ERR, "Error: spd.bin not found\n");
+		return -1;
+	}
+
+	if (len != region_device_sz(&spd_rdev)) {
+		printk(BIOS_ERR, "Error: spd.bin is not the correct size\n");
+		return -1;
+	}
+
+	if (rdev_readat(&spd_rdev, buf, 0, len) != len) {
+		printk(BIOS_ERR, "Error: couldn't read spd.bin\n");
+		return -1;
+	}
+
+	return 0;
+}

src/mainboard/google/kahlee/variants/grunt/Makefile.inc

@@ -0,0 +1,16 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Google, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+subdirs-y += spd

src/mainboard/google/kahlee/variants/grunt/spd/Makefile.inc

@@ -0,0 +1,26 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+## Copyright (C) 2015 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
+
+SPD_SOURCES =  empty				# 0b000
+SPD_SOURCES += empty				# 1b001
+SPD_SOURCES += empty				# 2b010
+SPD_SOURCES += empty				# 3b011
+SPD_SOURCES += empty				# 4b100
+SPD_SOURCES += empty				# 5b101
+SPD_SOURCES += empty				# 6b110
+SPD_SOURCES += empty				# 7b111

src/mainboard/google/kahlee/variants/grunt/spd/empty.spd.hex

@@ -0,0 +1,32 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

src/mainboard/google/kahlee/variants/kahlee/Makefile.inc

@@ -16,5 +16,6 @@
 bootblock-y += gpio.c
 
 romstage-y += gpio.c
+romstage-y += memory.c
 
 ramstage-y += gpio.c

src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h

@@ -19,14 +19,13 @@
 #ifndef __ACPI__
 #include <soc/gpio.h>
 
-#define MEM_CONFIG0	GPIO_135
-#define MEM_CONFIG1	GPIO_140
-#define MEM_CONFIG2	GPIO_144
 /*
- * Kahlee only uses 3 GPIOs to determine memory configuration, but other
+ * Kahlee doesn't use MEM_CONFIG GPIOs, but they are required to build
- * variants use 4. MEM_CONFIG3 must be defined so that the weak baseboard
+ * the baseboard weak memory_sku function.
- * version of the variant_board_id() function can compile.
  */
+#define MEM_CONFIG0	0
+#define MEM_CONFIG1	0
+#define MEM_CONFIG2	0
 #define MEM_CONFIG3	0
 
 /* SPI Write protect */

src/mainboard/google/kahlee/variants/kahlee/memory.c

@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+
+int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len)
+{
+	/* Return error so the default I2C SPD read is used */
+	return -1;
+}