Auto-declare chip_operations
The name is derived directly from the device path. Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
This commit is contained in:
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fee73df07a
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@ -17,7 +17,5 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations cpu_amd_agesa_family10_ops;
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struct cpu_amd_agesa_family10_config {
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};
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations cpu_amd_agesa_family12_ops;
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struct cpu_amd_agesa_family12_config {
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};
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations cpu_amd_agesa_family14_ops;
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struct cpu_amd_agesa_family14_config {
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};
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations cpu_amd_agesa_family15_ops;
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struct cpu_amd_agesa_family15_config {
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};
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations cpu_amd_agesa_family15tn_ops;
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struct cpu_amd_agesa_family15tn_config {
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};
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@ -1,4 +1,2 @@
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extern struct chip_operations cpu_amd_sc520_ops;
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struct cpu_amd_sc520_config {
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};
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@ -1,4 +1,2 @@
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extern struct chip_operations cpu_amd_socket_754_ops;
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struct cpu_amd_socket_754_config {
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};
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@ -1,4 +1,2 @@
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extern struct chip_operations cpu_amd_socket_939_ops;
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struct cpu_amd_socket_939_config {
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};
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@ -1,4 +1,2 @@
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extern struct chip_operations cpu_amd_socket_940_ops;
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struct cpu_amd_socket_940_config {
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};
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@ -1,4 +1,2 @@
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extern struct chip_operations cpu_amd_socket_AM2_ops;
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struct cpu_amd_socket_AM2_config {
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};
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations cpu_amd_socket_AM2r2_ops;
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struct cpu_amd_socket_AM2r2_config {
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};
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations cpu_amd_socket_AM3_ops;
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struct cpu_amd_socket_AM3_config {
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};
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations cpu_amd_socket_ASB2_ops;
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struct cpu_amd_socket_ASB2_config {
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};
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations cpu_amd_socket_C32_ops;
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struct cpu_amd_socket_C32_config {
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};
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extern struct chip_operations cpu_amd_socket_F_ops;
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struct cpu_amd_socket_F_config {
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};
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations cpu_amd_socket_F_1207_ops;
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struct cpu_amd_socket_F_1207_config {
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};
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extern struct chip_operations cpu_amd_socket_S1G1_ops;
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struct cpu_amd_socket_S1G1_config {
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};
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations cpu_intel_ep80579_ops;
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struct cpu_intel_ep80579_config {
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};
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations cpu_intel_model_206ax_ops;
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/* Magic value used to locate this chip in the device tree */
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#define SPEEDSTEP_APIC_MAGIC 0xACAC
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations cpu_intel_slot_1_ops;
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struct cpu_intel_slot_1_config {
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};
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extern struct chip_operations cpu_intel_slot_2_ops;
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struct cpu_intel_slot_2_config {
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};
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations cpu_intel_socket_441_ops;
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struct cpu_intel_socket_441_config {
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};
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extern struct chip_operations cpu_intel_socket_BGA956_ops;
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struct cpu_intel_socket_BGA956_config {
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};
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations cpu_intel_socket_FC_PGA370_ops;
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struct cpu_intel_socket_FC_PGA370_config {
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};
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extern struct chip_operations cpu_intel_socket_LGA771_ops;
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struct cpu_intel_socket_LGA771_config {
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};
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extern struct chip_operations cpu_intel_socket_PGA370_ops;
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struct cpu_intel_socket_PGA370_config {
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};
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extern struct chip_operations cpu_intel_socket_mFCBGA479_ops;
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struct cpu_intel_socket_mFCBGA479_config {
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};
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extern struct chip_operations cpu_intel_socket_mFCPGA478_ops;
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struct cpu_intel_socket_mFCPGA478_config {
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};
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extern struct chip_operations cpu_intel_socket_mPGA478_ops;
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struct cpu_intel_socket_mPGA478_config {
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};
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extern struct chip_operations cpu_intel_socket_mPGA479M_ops;
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struct cpu_intel_socket_mPGA479M_config {
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};
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extern struct chip_operations cpu_intel_socket_mPGA603_ops;
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struct cpu_intel_socket_mPGA603_config {
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};
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extern struct chip_operations cpu_intel_socket_mPGA604_ops;
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struct cpu_intel_socket_mPGA604_config {
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};
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extern struct chip_operations cpu_intel_socket_rPGA989_ops;
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struct cpu_intel_socket_rPGA989_config {
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};
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extern struct chip_operations drivers_generic_debug_ops;
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struct drivers_generic_debug_config {
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};
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#ifndef DRIVERS_GENERIC_IOAPIC_CHIP_H
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#define DRIVERS_GENERIC_IOAPIC_CHIP_H
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extern struct chip_operations drivers_generic_ioapic_ops;
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struct drivers_generic_ioapic_config {
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u32 version;
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u8 apicid;
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extern struct chip_operations drivers_i2c_adm1026_ops;
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struct drivers_i2c_adm1026_config {
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};
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extern struct chip_operations drivers_i2c_adm1027_ops;
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struct drivers_i2c_adm1027_config {
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};
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extern struct chip_operations drivers_i2c_adt7463_ops;
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struct drivers_i2c_adt7463_config {
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};
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extern struct chip_operations drivers_i2c_i2cmux_ops;
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struct drivers_i2c_i2cmux_config {
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};
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extern struct chip_operations drivers_i2c_i2cmux2_ops;
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struct drivers_i2c_i2cmux2_config {
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};
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extern struct chip_operations drivers_i2c_lm63_ops;
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struct drivers_i2c_lm63_config {
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};
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extern struct chip_operations drivers_i2c_w83793_ops;
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struct drivers_i2c_w83793_config {
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u8 mfc;
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u8 fanin;
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extern struct chip_operations drivers_i2c_w83795_ops;
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struct drivers_i2c_w83795_config {
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};
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* MA 02110-1301 USA
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*/
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extern struct chip_operations drivers_ics_954309_ops;
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struct drivers_ics_954309_config {
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u8 reg0;
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u8 reg1;
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#ifndef EC_LENOVO_H8EC_CHIP_H
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#define EC_LENOVO_H8EC_CHIP_H
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extern struct chip_operations ec_lenovo_h8_ops;
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struct ec_lenovo_h8_config {
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u8 config0;
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#ifndef EC_LENOVO_PMH7_CHIP_H
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#define EC_LENOVO_PMH7_CHIP_H
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extern struct chip_operations ec_lenovo_pmh7_ops;
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struct ec_lenovo_pmh7_config {
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int backlight_enable:1;
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int dock_event_enable:1;
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u16 mailbox_port;
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};
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struct chip_operations;
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extern struct chip_operations ec_smsc_mec1308_ops;
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#endif /* _EC_SMSC_MEC1308_CHIP_H */
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struct mainboard_emulation_qemu_x86_config {};
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extern struct chip_operations mainboard_emulation_qemu_x86_ops;
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{
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};
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extern struct chip_operations northbridge_amd_agesa_family10_ops;
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{
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};
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extern struct chip_operations northbridge_amd_agesa_family10_root_complex_ops;
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{
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};
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extern struct chip_operations northbridge_amd_agesa_family12_ops;
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{
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};
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extern struct chip_operations northbridge_amd_agesa_family12_root_complex_ops;
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{
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};
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extern struct chip_operations northbridge_amd_agesa_family14_ops;
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{
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};
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extern struct chip_operations northbridge_amd_agesa_family14_root_complex_ops;
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{
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};
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extern struct chip_operations northbridge_amd_agesa_family15_ops;
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{
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};
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extern struct chip_operations northbridge_amd_agesa_family15_root_complex_ops;
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{
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};
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extern struct chip_operations northbridge_amd_agesa_family15tn_ops;
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{
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};
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extern struct chip_operations northbridge_amd_agesa_family15tn_root_complex_ops;
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{
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};
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extern struct chip_operations northbridge_amd_amdfam10_ops;
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{
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};
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extern struct chip_operations northbridge_amd_amdfam10_root_complex_ops;
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{
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};
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extern struct chip_operations northbridge_amd_amdk8_ops;
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{
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};
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extern struct chip_operations northbridge_amd_amdk8_root_complex_ops;
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _CIMX_RD890_CHIP_H_
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#define _CIMX_RD890_CHIP_H_
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extern struct chip_operations northbridge_amd_cimx_rd890_ops;
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/**
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* RD890 specific device configuration
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*/
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{
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};
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extern struct chip_operations northbridge_amd_gx1_ops;
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};
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extern struct chip_operations northbridge_amd_gx2_ops;
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struct northbridge_amd_lx_config {
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};
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extern struct chip_operations northbridge_amd_lx_ops;
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{
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};
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extern struct chip_operations northbridge_intel_e7501_ops;
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@ -2,5 +2,3 @@ struct northbridge_intel_e7505_config
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{
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};
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extern struct chip_operations northbridge_intel_e7505_ops;
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@ -4,4 +4,3 @@ struct northbridge_intel_e7520_config
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unsigned int intrline;
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};
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extern struct chip_operations northbridge_intel_e7520_ops;
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unsigned int intrline;
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};
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extern struct chip_operations northbridge_intel_e7525_ops;
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u16 intrline;
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};
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extern struct chip_operations northbridge_intel_i3100_ops;
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@ -22,4 +22,3 @@ struct northbridge_intel_i440bx_config
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{
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};
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extern struct chip_operations northbridge_intel_i440bx_ops;
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@ -22,4 +22,3 @@ struct northbridge_intel_i440lx_config
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{
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};
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extern struct chip_operations northbridge_intel_i440lx_ops;
|
||||
|
|
|
@ -20,4 +20,3 @@
|
|||
struct northbridge_intel_i5000_config {
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_intel_i5000_ops;
|
||||
|
|
|
@ -21,4 +21,3 @@
|
|||
struct northbridge_intel_i82810_config {
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_intel_i82810_ops;
|
||||
|
|
|
@ -21,4 +21,3 @@
|
|||
struct northbridge_intel_i82830_config {
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_intel_i82830_ops;
|
||||
|
|
|
@ -22,4 +22,3 @@ struct northbridge_intel_i855_config
|
|||
{
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_intel_i855_ops;
|
||||
|
|
|
@ -20,4 +20,3 @@
|
|||
struct northbridge_intel_i945_config {
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_intel_i945_ops;
|
||||
|
|
|
@ -40,4 +40,3 @@ struct northbridge_intel_sandybridge_config {
|
|||
u32 gpu_pch_backlight; /* PCH Backlight PWM value */
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_intel_sandybridge_ops;
|
||||
|
|
|
@ -20,4 +20,3 @@
|
|||
struct northbridge_intel_sch_config {
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_intel_sch_ops;
|
||||
|
|
|
@ -21,4 +21,3 @@
|
|||
struct northbridge_rdc_r8610_config {
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_rdc_r8610_ops;
|
||||
|
|
|
@ -21,4 +21,3 @@
|
|||
struct northbridge_via_cn400_config {
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_via_cn400_ops;
|
||||
|
|
|
@ -21,4 +21,3 @@
|
|||
struct northbridge_via_cn700_config {
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_via_cn700_ops;
|
||||
|
|
|
@ -20,4 +20,3 @@
|
|||
struct northbridge_via_cx700_config {
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_via_cx700_ops;
|
||||
|
|
|
@ -2,4 +2,3 @@ struct northbridge_via_vt8601_config
|
|||
{
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_via_vt8601_ops;
|
||||
|
|
|
@ -2,4 +2,3 @@ struct northbridge_via_vt8623_config
|
|||
{
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_via_vt8623_ops;
|
||||
|
|
|
@ -20,4 +20,3 @@
|
|||
struct northbridge_via_vx800_config {
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_via_vx800_ops;
|
||||
|
|
|
@ -30,7 +30,5 @@ struct southbridge_amd_agesa_hudson_config
|
|||
u8 gpp_configuration;
|
||||
#endif
|
||||
};
|
||||
struct chip_operations;
|
||||
extern struct chip_operations southbridge_amd_agesa_hudson_ops;
|
||||
|
||||
#endif /* HUDSON_CHIP_H */
|
||||
|
|
|
@ -8,7 +8,4 @@ struct southbridge_amd_amd8111_config
|
|||
unsigned int phy_lowreset : 1;
|
||||
};
|
||||
|
||||
struct chip_operations;
|
||||
extern struct chip_operations southbridge_amd_amd8111_ops;
|
||||
|
||||
#endif /* AMD8111_CHIP_H */
|
||||
|
|
|
@ -20,8 +20,6 @@
|
|||
#ifndef _CIMX_SB700_CHIP_H_
|
||||
#define _CIMX_SB700_CHIP_H_
|
||||
|
||||
extern struct chip_operations southbridge_amd_cimx_sb700_ops;
|
||||
|
||||
/*
|
||||
* configuration set in mainboard/devicetree.cb
|
||||
* boot_switch_sata_ide:
|
||||
|
|
|
@ -20,8 +20,6 @@
|
|||
#ifndef _CIMX_SB800_CHIP_H_
|
||||
#define _CIMX_SB800_CHIP_H_
|
||||
|
||||
extern struct chip_operations southbridge_amd_cimx_sb800_ops;
|
||||
|
||||
/*
|
||||
* configuration set in mainboard/devicetree.cb
|
||||
* boot_switch_sata_ide:
|
||||
|
|
|
@ -20,8 +20,6 @@
|
|||
#ifndef _CIMX_SB900_CHIP_H_
|
||||
#define _CIMX_SB900_CHIP_H_
|
||||
|
||||
extern struct chip_operations southbridge_amd_cimx_sb900_ops;
|
||||
|
||||
/*
|
||||
* configuration set in mainboard/devicetree.cb
|
||||
* boot_switch_sata_ide:
|
||||
|
|
|
@ -21,8 +21,6 @@
|
|||
#ifndef SOUTHBRIDGE_AMD_CS5530_CHIP_H
|
||||
#define SOUTHBRIDGE_AMD_CS5530_CHIP_H
|
||||
|
||||
extern struct chip_operations southbridge_amd_cs5530_ops;
|
||||
|
||||
struct southbridge_amd_cs5530_config {
|
||||
int ide0_enable:1;
|
||||
int ide1_enable:1;
|
||||
|
|
|
@ -1,8 +1,6 @@
|
|||
#ifndef _SOUTHBRIDGE_AMD_CS5535
|
||||
#define _SOUTHBRIDGE_AMD_CS5535
|
||||
|
||||
extern struct chip_operations southbridge_amd_cs5535_ops;
|
||||
|
||||
struct southbridge_amd_cs5535_config {
|
||||
int setupflash;
|
||||
};
|
||||
|
|
|
@ -23,8 +23,6 @@
|
|||
|
||||
#define MAX_UNWANTED_VPCI 8 /* increase if needed */
|
||||
|
||||
extern struct chip_operations southbridge_amd_cs5536_ops;
|
||||
|
||||
struct southbridge_amd_cs5536_config {
|
||||
unsigned int lpc_serirq_enable; /* interrupt enables for LPC bus; each bit is an irq 0-15 */
|
||||
unsigned int lpc_serirq_polarity; /* LPC IRQ polarity; each bit is an irq 0-15 */
|
||||
|
|
|
@ -33,7 +33,5 @@ struct southbridge_amd_rs690_config
|
|||
u8 gfx_reconfiguration; /* Dynamic Lind Width Control */
|
||||
u8 gfx_link_width; /* Desired width of lane 2 */
|
||||
};
|
||||
struct chip_operations;
|
||||
extern struct chip_operations southbridge_amd_rs690_ops;
|
||||
|
||||
#endif /* RS690_CHIP_H */
|
||||
|
|
|
@ -36,7 +36,5 @@ struct southbridge_amd_rs780_config
|
|||
u8 gfx_pcie_config; /* GFX PCIE Modes */
|
||||
u8 gfx_ddi_config; /* GFX DDI Modes */
|
||||
};
|
||||
struct chip_operations;
|
||||
extern struct chip_operations southbridge_amd_rs780_ops;
|
||||
|
||||
#endif /* RS780_CHIP_H */
|
||||
|
|
|
@ -24,7 +24,5 @@ struct southbridge_amd_sb600_config
|
|||
{
|
||||
u32 hda_viddid;
|
||||
};
|
||||
struct chip_operations;
|
||||
extern struct chip_operations southbridge_amd_sb600_ops;
|
||||
|
||||
#endif /* SB600_CHIP_H */
|
||||
|
|
|
@ -24,7 +24,5 @@ struct southbridge_amd_sb700_config
|
|||
{
|
||||
u32 boot_switch_sata_ide : 1;
|
||||
};
|
||||
struct chip_operations;
|
||||
extern struct chip_operations southbridge_amd_sb700_ops;
|
||||
|
||||
#endif /* SB700_CHIP_H */
|
||||
|
|
|
@ -28,7 +28,5 @@ struct southbridge_amd_sb800_config
|
|||
u32 hda_viddid;
|
||||
u8 gpp_configuration;
|
||||
};
|
||||
struct chip_operations;
|
||||
extern struct chip_operations southbridge_amd_sb800_ops;
|
||||
|
||||
#endif /* SB800_CHIP_H */
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue