mainboard/asus/kfsn4-dre: Enable BIOS recovery jumper
The ASUS KFSN4-DRE has a physical BIOS recovery jumper; force coreboot into fallback mode if that jumper is set. Change-Id: I513299c3e3261fc76133a49813685d48c53a172a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9156 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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@ -28,6 +28,10 @@ config MAINBOARD_DIR
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string
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default asus/kfsn4-dre
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config BOOTBLOCK_MAINBOARD_INIT
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string
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default "mainboard/asus/kfsn4-dre/bootblock.c"
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config DCACHE_RAM_BASE
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hex
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default 0xc4000
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@ -0,0 +1,85 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <pc80/mc146818rtc.h>
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#include <superio/winbond/common/winbond.h>
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#include <superio/winbond/w83627thg/w83627thg.h>
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#define GPIO_DEV PNP_DEV(0x2e, W83627THG_GPIO3)
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#define WINBOND_ENTRY_KEY 0x87
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#define WINBOND_EXIT_KEY 0xAA
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/* Enable configuration: pass entry key '0x87' into index port dev. */
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static void pnp_enter_conf_state(pnp_devfn_t dev)
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{
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u16 port = dev >> 8;
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outb(WINBOND_ENTRY_KEY, port);
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outb(WINBOND_ENTRY_KEY, port);
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}
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/* Disable configuration: pass exit key '0xAA' into index port dev. */
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static void pnp_exit_conf_state(pnp_devfn_t dev)
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{
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u16 port = dev >> 8;
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outb(WINBOND_EXIT_KEY, port);
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}
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uint8_t bootblock_read_recovery_jumper(pnp_devfn_t dev)
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{
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uint8_t recovery_enabled = 0;
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pnp_enter_conf_state(dev);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 1); /* Enable GPIO3 */
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pnp_write_config(dev, 0xf0, 0xff); /* Set GPIO3 to input */
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recovery_enabled = !(pnp_read_config(dev, 0xf1) & 0x08); /* Read GP33 */
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pnp_exit_conf_state(dev);
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return recovery_enabled;
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}
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void bootblock_mainboard_init(void)
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{
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uint8_t recovery_enabled;
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unsigned char addr;
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unsigned char byte;
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recovery_enabled = bootblock_read_recovery_jumper(GPIO_DEV);
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if (recovery_enabled) {
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#if CONFIG_USE_OPTION_TABLE
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/* Clear NVRAM checksum */
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for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
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cmos_write(0x0, addr);
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}
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/* Set fallback boot */
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byte = cmos_read(RTC_BOOT_BYTE);
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byte &= 0xfc;
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cmos_write(byte, RTC_BOOT_BYTE);
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#else
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/* FIXME
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* Figure out how to recover if the option table is not available
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*/
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#endif
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}
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}
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@ -47,6 +47,9 @@ Power LED (-) is connected to U15 (SuperIO) pin 64 via U4 pins 5,6 and a small M
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ID LED (-) is connected to a ??? via U4 pins 1,2,3,4 and U77 pins 5,6
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It appears that setting U15 (SuperIO) pin 88 LOW will override the ID LED and force it ON
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RECOVERY2 middle pin is connected to U15 (SuperIO) pin 89
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Normal is HIGH, recovery is LOW.
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PCIe slot WAKE# connects to U7 pin E23 (PCIE_WAKE#)
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CPU_WARN1 is driven by (???) via a simple buffer (U13 pin 10)
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