From fefc77afd0e739ec18129f8cd58781e15b9802e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Tue, 21 Jun 2016 19:37:03 +0200 Subject: [PATCH] arch/riscv: Show fault PC and load address on load access faults MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ib0535bf25ce25550cc17f64177f804a70aa13fb3 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/15286 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/riscv/trap_handler.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index ff3be56f78..5b4d0b1801 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -122,6 +122,8 @@ void trap_handler(trapframe *tf) { break; case 5: printk(BIOS_DEBUG, "Trap: Load access fault\n"); + printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); + printk(BIOS_DEBUG, "Load Address: %p\n", badAddr); break; case 6: printk(BIOS_DEBUG, "Trap: Store address misaligned\n");