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intel/kunimitsu: Enable FspSkipMpInit token 

MP init is already handled in coreboot, but it is also part of FSP
FSP has a implemented a provision to allow FSP to skip MP init and
let coreboot handle it.

BRANCH=none
BUG=chrome-os-partner:44805
TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB.

CQ-DEPEND=CL:310192

Change-Id: Idd9b1424f23765ce227005a322ac72d9e9fc841a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5c52d0f0cc5d480c87fababc3316009e3ade6e45
Original-Change-Id: I9d92046d0237680b8d562814a9a605a36efb9516
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/312926
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12992
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Rizwan Qureshi 2015-11-19 16:30:18 +05:30 committed by Patrick Georgi
parent 497ff3ce7c
commit fefce18533
1 changed files with 2 additions and 0 deletions
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2
src/mainboard/intel/kunimitsu/devicetree.cb
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@ -126,6 +126,8 @@ chip soc/intel/skylake
.voltage_limit = 0x5F0 \
}"
register "FspSkipMpInit" = "1"
# Enable Root port 1 and 5.
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[4]" = "1"