From fefd00043186d3b405f58be3daaa2312fdf3ef9e Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Thu, 31 Mar 2022 15:56:01 +0800 Subject: [PATCH] soc/mediatek/mt8195: Configure SCP core 2 domain setting SCP core 2 is enabled for MT8195 camera feature. It requires the same register access permission as SCP core 1. Therefore, we configure the same domain ID for both cores. BRANCH=cherry BUG=b:193814857 TEST=cherry boot ok Signed-off-by: Tinghan Shen Change-Id: Idf335593936b12c083c926a252fa99c3b76cda6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64575 Reviewed-by: Rex-BC Chen Reviewed-by: Yu-Ping Wu Reviewed-by: Yidi Lin Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8195/devapc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/mediatek/mt8195/devapc.c b/src/soc/mediatek/mt8195/devapc.c index ac3e6db8d6..2c41ff5d4a 100644 --- a/src/soc/mediatek/mt8195/devapc.c +++ b/src/soc/mediatek/mt8195/devapc.c @@ -1955,7 +1955,9 @@ static void infra2_init(uintptr_t base) static void scp_master_init(uintptr_t base) { - write32(getreg(base, SCP_DOM), DOMAIN_3); + SET32_BITFIELDS(getreg(base, SCP_DOM), + FOUR_BIT_DOM_REMAP_0, DOMAIN_3, + FOUR_BIT_DOM_REMAP_1, DOMAIN_3); write32(getreg(base, ADSP_DOM), DOMAIN_4); /* Let SCP_DOM and ADSP_DOM registers be read-only for security */