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soc/mediatek/mt8195: Configure SCP core 2 domain setting 

SCP core 2 is enabled for MT8195 camera feature. It requires the same
register access permission as SCP core 1. Therefore, we configure the
same domain ID for both cores.

BRANCH=cherry
BUG=b:193814857
TEST=cherry boot ok

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Change-Id: Idf335593936b12c083c926a252fa99c3b76cda6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64575
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tinghan Shen 2022-03-31 15:56:01 +08:00 committed by Felix Held
parent 453f841b2e
commit fefd000431
1 changed files with 3 additions and 1 deletions
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4
src/soc/mediatek/mt8195/devapc.c
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@ -1955,7 +1955,9 @@ static void infra2_init(uintptr_t base)
static void scp_master_init(uintptr_t base)
{
write32(getreg(base, SCP_DOM), DOMAIN_3);
SET32_BITFIELDS(getreg(base, SCP_DOM),
FOUR_BIT_DOM_REMAP_0, DOMAIN_3,
FOUR_BIT_DOM_REMAP_1, DOMAIN_3);
write32(getreg(base, ADSP_DOM), DOMAIN_4);
/* Let SCP_DOM and ADSP_DOM registers be read-only for security */