ChromeOS: Refactor ACPI CNVS generation

Remove chromeos_dsdt_generator() calls under mainboard, it
is possible to make the single call to fill \CNVS and
\OIPG without leveraging device operations.

Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Kyösti Mälkki 2021-06-13 15:57:06 +03:00 committed by Felix Held
parent ad489b8a27
commit ff01bca624
51 changed files with 15 additions and 143 deletions

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@ -11,7 +11,3 @@
External (GNVS, OpRegionObj)
External (DNVS, OpRegionObj)
#endif
#if CONFIG(CHROMEOS_NVS)
External (CNVS, OpRegionObj)
#endif

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@ -4,7 +4,6 @@
#if CONFIG(CHROMEOS_NVS)
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif

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@ -24,7 +24,7 @@
#include <timer.h>
#include <timestamp.h>
#include <types.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <version.h>
static boot_state_t bs_pre_device(void *arg);

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@ -7,7 +7,6 @@
#include <soc/acpi.h>
#include <string.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
/*
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
@ -95,8 +94,6 @@ static void mainboard_enable(struct device *dev)
init_tables();
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {

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@ -2,7 +2,6 @@
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#include "variant.h"
@ -29,7 +28,6 @@ static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}

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@ -4,7 +4,6 @@
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
@ -25,7 +24,6 @@ static void mainboard_init(struct device *dev)
static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {

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@ -5,7 +5,6 @@
#include <device/device.h>
#include <ec/ec.h>
#include <soc/ramstage.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <fw_config.h>
static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
@ -60,7 +59,6 @@ static void mainboard_dev_init(struct device *dev)
static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_dev_init;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
dev->ops->get_smbios_strings = mainboard_smbios_strings;
}

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@ -14,7 +14,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <smbios.h>
#include <ec/quanta/ene_kb3940q/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
static unsigned int search(char *p, char *a, unsigned int lengthp,
unsigned int lengtha)
@ -258,7 +257,6 @@ static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = butterfly_onboard_smbios_data;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}

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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
static void mainboard_init(struct device *dev)
@ -16,7 +15,6 @@ static void mainboard_init(struct device *dev)
static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {

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@ -9,7 +9,6 @@
#include <security/tpm/tss.h>
#include <soc/soc_chip.h>
#include <vb2_api.h>
#include <vendorcode/google/chromeos/chromeos.h>
static void mainboard_update_soc_chip_config(void)
{
@ -68,7 +67,6 @@ static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_dev_init;
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {

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@ -4,14 +4,8 @@
#include <baseboard/variants.h>
#include <device/device.h>
#include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <variant/gpio.h>
static void mainboard_enable(struct device *dev)
{
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
static void mainboard_chip_init(void *chip_info)
{
const struct pad_config *base_pads;
@ -26,5 +20,4 @@ static void mainboard_chip_init(void *chip_info)
struct chip_operations mainboard_ops = {
.init = mainboard_chip_init,
.enable_dev = mainboard_enable,
};

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@ -4,7 +4,6 @@
#include <smbios.h>
#include <soc/ramstage.h>
#include <variant/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
/* mainboard silk screen shows DIMM-A and DIMM-B */
void smbios_fill_dimm_locator(const struct dimm_info *dimm,
@ -32,12 +31,6 @@ static void mainboard_init(void *chip_info)
gpio_configure_pads(gpio_table, num_gpios);
}
static void mainboard_enable(struct device *dev)
{
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,
};

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@ -4,7 +4,6 @@
#include <console/console.h>
#include <device/device.h>
#include <ec/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/nhlt.h>
#include "gpio.h"
@ -58,7 +57,6 @@ static unsigned long mainboard_write_acpi_tables(
static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
}

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@ -17,7 +17,6 @@
#include <soc/nhlt.h>
#include <string.h>
#include <timer.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <variant/gpio.h>
@ -223,7 +222,6 @@ static void mainboard_enable(struct device *dev)
mainboard_set_power_limits(soc_conf);
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
}

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@ -7,7 +7,6 @@
#include <gpio.h>
#include <soc/nhlt.h>
#include <variant/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
static const char *oem_id_maxim = "INTEL";
@ -96,7 +95,6 @@ static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
static void mainboard_chip_init(void *chip_info)

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@ -10,7 +10,6 @@
#include <gpio.h>
#include <soc/acpi.h>
#include <variant/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
#define BACKLIGHT_GPIO GPIO_129
#define WWAN_AUX_RST_GPIO GPIO_18
@ -197,7 +196,6 @@ static void mainboard_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
init_tables();

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@ -6,7 +6,6 @@
#include <soc/gpio.h>
#include <soc/ramstage.h>
#include <variant/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
void mainboard_silicon_init_params(FSPS_UPD *supd)
{
@ -36,7 +35,6 @@ static void mainboard_init(struct device *dev)
static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
variant_mainboard_enable(dev);
}

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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
static void mainboard_init(struct device *dev)
@ -15,7 +14,6 @@ static void mainboard_init(struct device *dev)
static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {

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@ -17,7 +17,6 @@
#include <amdblocks/acpimmio.h>
#include <variant/ec.h>
#include <variant/thermal.h>
#include <vendorcode/google/chromeos/chromeos.h>
/***********************************************************
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
@ -147,7 +146,6 @@ static void mainboard_enable(struct device *dev)
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
int mainboard_get_xhci_oc_map(uint16_t *map)

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@ -16,7 +16,6 @@
#include <southbridge/intel/common/gpio.h>
#include <smbios.h>
#include <ec/google/chromeec/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
#if CONFIG(VGA_ROM_RUN)
static int int15_handler(void)
@ -170,7 +169,6 @@ static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = link_onboard_smbios_data;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
#if CONFIG(VGA_ROM_RUN)
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);

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@ -20,7 +20,6 @@
#include <soc/nhlt.h>
#include <soc/pci_devs.h>
#include <stdint.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <variant/ec.h>
#include <variant/gpio.h>
@ -140,7 +139,6 @@ static unsigned long mainboard_write_acpi_tables(
static void mainboard_enable(struct device *dev)
{
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {

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@ -10,7 +10,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <smbios.h>
#include <ec/compal/ene932/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
void mainboard_suspend_resume(void)
{
@ -61,7 +60,6 @@ static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = parrot_onboard_smbios_data;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}

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@ -6,7 +6,6 @@
#include <ec/ec.h>
#include <soc/pci_devs.h>
#include <soc/nhlt.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <variant/gpio.h>
@ -47,7 +46,6 @@ static unsigned long mainboard_write_acpi_tables(const struct device *device,
static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
}

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@ -8,7 +8,6 @@
#include <soc/gpio.h>
#include <soc/int15.h>
#include <bootstate.h>
#include <vendorcode/google/chromeos/chromeos.h>
static void mainboard_init(struct device *dev)
{
@ -54,7 +53,6 @@ static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
/* Install custom int15 handler for VGA OPROM */
if (CONFIG(VGA_ROM_RUN))

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@ -12,7 +12,6 @@
#include <soc/gpio.h>
#include <soc/nhlt.h>
#include <string.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <variant/ec.h>
#include <variant/gpio.h>
@ -125,7 +124,6 @@ static unsigned long mainboard_write_acpi_tables(
static void mainboard_enable(struct device *dev)
{
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {

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@ -5,7 +5,6 @@
#include <smbios.h>
#include <soc/gpio.h>
#include <variant/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
#if CONFIG(GENERATE_SMBIOS_TABLES)
/* mainboard silk screen shows DIMM-A and DIMM-B */
@ -46,12 +45,6 @@ static void mainboard_init(void *chip_info)
gpio_configure_pads(gpio_unused, ARRAY_SIZE(gpio_unused));
}
static void mainboard_enable(struct device *dev)
{
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,
};

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@ -6,7 +6,6 @@
#include <drivers/intel/gma/int15.h>
#include <acpi/acpi.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#include "onboard.h"
@ -66,7 +65,6 @@ static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}

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@ -6,7 +6,6 @@
#include <acpi/acpi.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <ec/quanta/it8518/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#include "onboard.h"
@ -42,7 +41,6 @@ static void mainboard_init(struct device *dev)
static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}

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@ -14,7 +14,6 @@
#include <soc/gpio.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <variant/gpio.h>
#include <vb2_api.h>
@ -78,7 +77,6 @@ static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t
static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
dev->ops->get_smbios_strings = mainboard_smbios_strings;
variant_ramstage_init();

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@ -23,7 +23,6 @@
#include <amdblocks/acpimmio.h>
#include <variant/ec.h>
#include <variant/thermal.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <commonlib/helpers.h>
#define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN"
@ -203,7 +202,6 @@ static void mainboard_enable(struct device *dev)
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
}

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@ -6,7 +6,6 @@
#include <drivers/intel/gma/opregion.h>
#include <ec/ec.h>
#include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <smbios.h>
#include <stdint.h>
#include <string.h>
@ -57,8 +56,6 @@ static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t
static void mainboard_enable(struct device *dev)
{
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
#if CONFIG(BOARD_INTEL_ADLRVP_M_EXT_EC)
dev->ops->get_smbios_strings = mainboard_smbios_strings;
#endif

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@ -5,7 +5,6 @@
#include <drivers/intel/gma/int15.h>
#include <acpi/acpi.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <vendorcode/google/chromeos/chromeos.h>
void mainboard_suspend_resume(void)
{
@ -18,7 +17,6 @@ void mainboard_suspend_resume(void)
static void mainboard_enable(struct device *dev)
{
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}

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@ -6,7 +6,6 @@
#include <nhlt.h>
#include <soc/gpio.h>
#include <soc/nhlt.h>
#include <vendorcode/google/chromeos/chromeos.h>
static void mainboard_init(void *chip_info)
{
@ -45,7 +44,6 @@ static unsigned long mainboard_write_acpi_tables(const struct device *device,
static void mainboard_enable(struct device *dev)
{
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {

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@ -4,14 +4,12 @@
#include <drivers/intel/gma/int15.h>
#include <acpi/acpi.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <vendorcode/google/chromeos/chromeos.h>
// mainboard_enable is executed as first thing after
// enumerate_buses().
static void mainboard_enable(struct device *dev)
{
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}

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@ -9,7 +9,6 @@
#include <nhlt.h>
#include <soc/gpio.h>
#include <soc/nhlt.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <variant/ec.h>
#include <variant/gpio.h>
@ -55,7 +54,6 @@ static unsigned long mainboard_write_acpi_tables(
static void mainboard_enable(struct device *dev)
{
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {

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@ -5,7 +5,6 @@
#include <baseboard/variants.h>
#include <device/device.h>
#include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
static void mainboard_init(void *chip_info)
{
@ -16,12 +15,6 @@ static void mainboard_init(void *chip_info)
gpio_configure_pads(pads, num);
}
static void mainboard_enable(struct device *dev)
{
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,
};

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@ -7,7 +7,6 @@
#include <soc/gpio.h>
#include <soc/pcr_ids.h>
#include <smbios.h>
#include <vendorcode/google/chromeos/chromeos.h>
#define SERIAL_IO_PCR_GPPRVRW4 0x60C
@ -23,11 +22,6 @@ static void mainboard_init(void *chip_info)
pcr_write32(PID_SERIALIO, SERIAL_IO_PCR_GPPRVRW4, BIT8);
}
static void mainboard_enable(struct device *dev)
{
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
const char *smbios_system_sku(void)
{
static const char *sku_str = "sku2147483647"; /* sku{0-1} */
@ -36,5 +30,4 @@ const char *smbios_system_sku(void)
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,
};

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@ -4,7 +4,6 @@
#include <device/device.h>
#include <gpio.h>
#include <soc/nhlt.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#include <variant/gpio.h>
@ -21,7 +20,6 @@ static void mainboard_init(struct device *dev)
static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {

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@ -5,7 +5,6 @@
#include <device/device.h>
#include <gpio.h>
#include <soc/nhlt.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
#include "gpio.h"
@ -82,7 +81,6 @@ static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {

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@ -5,7 +5,6 @@
#include <device/device.h>
#include <ec/ec.h>
#include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
static void mainboard_init(void *chip_info)
{
@ -21,12 +20,6 @@ static void mainboard_init(void *chip_info)
mainboard_ec_init();
}
static void mainboard_enable(struct device *dev)
{
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,
};

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@ -2,7 +2,6 @@
#include <device/device.h>
#include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
static void mainboard_init(struct device *dev)
@ -17,7 +16,6 @@ static void mainboard_init(struct device *dev)
static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {

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@ -5,7 +5,6 @@
#include <device/device.h>
#include <ec/ec.h>
#include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <smbios.h>
#include <string.h>
@ -29,12 +28,6 @@ static void mainboard_init(void *chip_info)
mainboard_ec_init();
}
static void mainboard_enable(struct device *dev)
{
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,
};

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@ -2,14 +2,12 @@
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
#include <vendorcode/google/chromeos/chromeos.h>
// mainboard_enable is executed as first thing after
// enumerate_buses().
static void mainboard_enable(struct device *dev)
{
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}

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@ -10,7 +10,6 @@
#include "onboard.h"
#include <southbridge/intel/bd82x6x/pch.h>
#include <smbios.h>
#include <vendorcode/google/chromeos/chromeos.h>
void mainboard_suspend_resume(void)
{
@ -73,7 +72,6 @@ static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = lumpy_onboard_smbios_data;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}

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@ -4,14 +4,12 @@
#include <drivers/intel/gma/int15.h>
#include <acpi/acpi.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <vendorcode/google/chromeos/chromeos.h>
// mainboard_enable is executed as first thing after
// enumerate_buses().
static void mainboard_enable(struct device *dev)
{
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}

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@ -33,8 +33,3 @@ void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num)
acpigen_pop_len();
}
void chromeos_dsdt_generator(const struct device *dev)
{
mainboard_chromeos_acpi_generate();
}

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@ -97,4 +97,6 @@ Device (CRHW)
}
}
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
#include "ramoops.asl"

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@ -1,9 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This is the ChromeOS specific ACPI information needed by
* the mainboard's chromeos.asl
* chromeos.asl
*/
External (CNVS, OpRegionObj)
Field (CNVS, ByteAcc, NoLock, Preserve)
{
VBT0, 32, // 0x000 - Boot Reason

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@ -26,6 +26,7 @@ void cbmem_add_vpd_calibration_data(void);
void chromeos_set_me_hash(u32*, int);
void chromeos_set_ramoops(void *ram_oops, size_t size);
void chromeos_set_ecfw_rw(void);
void chromeos_init_chromeos_acpi(void);
/**
* get_dsm_calibration_from_key - Gets value related to DSM calibration from VPD
@ -45,16 +46,9 @@ struct cros_gpio;
void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num);
/*
* Common helper function and delcarations for mainboards to use to generate
* ACPI-specific Chrome OS needs.
* Declaration for mainboards to use to generate ACPI-specific Chrome OS needs.
*/
void mainboard_chromeos_acpi_generate(void);
#if CONFIG(CHROMEOS)
struct device;
void chromeos_dsdt_generator(const struct device *dev);
#else
#define chromeos_dsdt_generator NULL
#endif
enum {
CROS_GPIO_REC = 1, /* Recovery */

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@ -98,7 +98,14 @@ void acpi_fill_cnvs(void)
{
const struct opregion cnvs_op = OPREGION("CNVS", SYSTEMMEMORY, (uintptr_t)chromeos_acpi,
sizeof(*chromeos_acpi));
if (!chromeos_acpi)
return;
acpigen_write_scope("\\");
acpigen_write_opregion(&cnvs_op);
acpigen_pop_len();
/* Usually this creates OIPG package for GPIOs. */
mainboard_chromeos_acpi_generate();
}

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@ -32,6 +32,4 @@ struct chromeos_acpi {
u8 pad[298]; // dd6-eff
} __packed;
void chromeos_init_chromeos_acpi(void);
#endif