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broadwell: Add configuration for tuning VR for C-state operations 

Add some configuration options that allow tuning the VR for C-state
settings that may be able to reduce noise.

- Add option to enable slow VR ramp rate for C-state exit
- Add variable to configure the minimum C6/C7 voltage

BUG=chrome-os-partner:34771
BRANCH=broadwell
TEST=build and boot on samus

Change-Id: I01445d62fbfcf200b787b924d8d72685819a4715
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: ed8f355e60292c82791817ae31bff58ac2390a72
Original-Change-Id: I8af75b69c8b55d3e210170ee96f8e22c2fd76374
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241950
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9497
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Duncan Laurie 2015-01-20 07:53:27 -08:00 committed by Stefan Reinauer
parent ba081ef50d
commit ff0f460e76
2 changed files with 38 additions and 4 deletions
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22
src/soc/intel/broadwell/chip.h
View File

@ -130,6 +130,28 @@ struct soc_intel_broadwell_config {
/* Enable S0iX support */
int s0ix_enable;
/*
* Minimum voltage for C6/C7 state:
* 0x67 = 1.6V (full swing)
* ...
* 0x79 = 1.7V
* ...
* 0x83 = 1.8V (no swing)
*/
int vr_cpu_min_vid;
/*
* Set slow VR ramp rate on C-state exit:
* 0 = Fast VR ramp rate / 2
* 1 = Fast VR ramp rate / 4
* 2 = Fast VR ramp rate / 8
* 3 = Fast VR ramp rate / 16
*/
int vr_slow_ramp_rate_set;
/* Enable slow VR ramp rate */
int vr_slow_ramp_rate_enable;
/* Deep SX enable */
int deep_sx_enable_ac;
int deep_sx_enable_dc;

18
src/soc/intel/broadwell/cpu.c
View File

@ -180,6 +180,8 @@ static u32 pcode_mailbox_read(u32 command)
static void initialize_vr_config(void)
{
device_t dev = SA_DEV_ROOT;
config_t *conf = dev->chip_info;
msr_t msr;
printk(BIOS_DEBUG, "Initializing VR config.\n");
@ -203,17 +205,27 @@ static void initialize_vr_config(void)
msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
/* Set IOUT_OFFSET to 0. */
msr.hi &= ~0xff;
/* Set exit ramp rate to fast. */
msr.hi |= (1 << (50 - 32));
/* Set entry ramp rate to slow. */
msr.hi &= ~(1 << (51 - 32));
/* Enable decay mode on C-state entry. */
msr.hi |= (1 << (52 - 32));
/* Set the slow ramp rate to be fast ramp rate / 4 */
/* Set the slow ramp rate */
msr.hi &= ~(0x3 << (53 - 32));
/* Configure the C-state exit ramp rate. */
if (conf->vr_slow_ramp_rate_enable) {
/* Configured slow ramp rate. */
msr.hi |= ((conf->vr_slow_ramp_rate_set & 0x3) << (53 - 32));
/* Set exit ramp rate to slow. */
msr.hi &= ~(1 << (50 - 32));
} else {
/* Fast ramp rate / 4. */
msr.hi |= (0x01 << (53 - 32));
/* Set exit ramp rate to fast. */
msr.hi |= (1 << (50 - 32));
}
/* Set MIN_VID (31:24) to allow CPU to have full control. */
msr.lo &= ~0xff000000;
msr.lo |= (conf->vr_cpu_min_vid & 0xff) << 24;
wrmsr(MSR_VR_MISC_CONFIG, msr);
/* Configure VR_MISC_CONFIG2 MSR. */