nb/gm45,x4x/gma.c remove writes to nonexisting FDI registers
This removes writes to FDI related registers since there is no FDI link on these targets. This is likely a remainder from copying code from later targets. TESTED on Thinkpad x200 (gm45) Change-Id: Id67fdc999185fa184a9ff0e5c3fc9bced04131ad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16993 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
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@ -305,14 +305,8 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
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write32(mmio + PIPE_LINK_M1(0), link_m1);
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write32(mmio + PIPE_LINK_N1(0), link_n1);
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write32(mmio + 0x000f000c, 0x00002040);
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mdelay(1);
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write32(mmio + 0x000f000c, 0x00002050);
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write32(mmio + 0x00060100, 0x00044000);
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mdelay(1);
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write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
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write32(mmio + 0x000f0008, 0x00000040);
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write32(mmio + 0x000f000c, 0x00022050);
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write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
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write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
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@ -598,14 +592,8 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
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write32(mmio + PIPE_LINK_M1(0), link_m1);
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write32(mmio + PIPE_LINK_N1(0), link_n1);
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write32(mmio + 0x000f000c, 0x00002040);
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mdelay(1);
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write32(mmio + 0x000f000c, 0x00002050);
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write32(mmio + 0x00060100, 0x00044000);
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mdelay(1);
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write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
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write32(mmio + 0x000f0008, 0x00000040);
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write32(mmio + 0x000f000c, 0x00022050);
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write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
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write32(mmio + PIPECONF(0), PIPECONF_ENABLE
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| PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
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@ -311,14 +311,8 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
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write32(mmio + PIPE_LINK_M1(0), link_m1);
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write32(mmio + PIPE_LINK_N1(0), link_n1);
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write32(mmio + 0x000f000c, 0x00002040);
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mdelay(1);
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write32(mmio + 0x000f000c, 0x00002050);
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write32(mmio + 0x00060100, 0x00044000);
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mdelay(1);
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write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
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write32(mmio + 0x000f0008, 0x00000040);
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write32(mmio + 0x000f000c, 0x00022050);
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write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
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write32(mmio + PIPECONF(0), PIPECONF_ENABLE
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| PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
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