diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c
index 3388322aa5..b9cfa2023a 100644
--- a/src/mainboard/apple/macbookair4_2/early_southbridge.c
+++ b/src/mainboard/apple/macbookair4_2/early_southbridge.c
@@ -41,12 +41,10 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	/* Disable devices.  */
 	RCBA32(0x3414) = 0x00000020;
-	RCBA32(0x3418) = 0x1ffc0ee3;
-
 }
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },
diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c
index f556443e96..645fd0800c 100644
--- a/src/mainboard/asrock/b75pro3-m/romstage.c
+++ b/src/mainboard/asrock/b75pro3-m/romstage.c
@@ -27,9 +27,8 @@ void pch_enable_lpc(void)
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c
index 4516ac22ba..69492462be 100644
--- a/src/mainboard/compulab/intense_pc/romstage.c
+++ b/src/mainboard/compulab/intense_pc/romstage.c
@@ -47,12 +47,9 @@ void pch_enable_lpc(void)
 #endif
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable devices. */
 	RCBA32(0x3414) = 0x00000000;
-	RCBA32(0x3418) = 0x16e81fe3;
-
 }
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 },
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
index cbc55921a8..5a2c935d5a 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -61,7 +61,7 @@ static void it8728f_b75md3h_disable_reboot(pnp_devfn_t dev)
 	ite_reg_write(IT8728F_EC, 0x30, 0x01);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 /*
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
@@ -131,9 +131,6 @@ void rcba_config(void)
 	RCBA32(0x3844) = 0x0000e5e4;
 	RCBA32(0x3848) = 0x0000000e;
 */
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x17ee1fe1;
-
 	/* Enable HECI */
 	RCBA32(FD2) &= ~0x2;
 }
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
index 22a10aef4d..a389e68f0d 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
@@ -61,11 +61,8 @@ static void it8728f_b75md3v_disable_reboot(pnp_devfn_t dev)
 	ite_reg_write(IT8728F_EC, 0x30, 0x01);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x17ee1fe1;
-
 	/* Enable HECI */
 	RCBA32(FD2) &= ~0x2;
 }
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 50e037f74e..3ef4659a5a 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -53,7 +53,7 @@ void pch_enable_lpc(void)
 
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	u32 reg32;
 
@@ -101,7 +101,6 @@ void rcba_config(void)
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
 	/* Disable PCI bridge so MRC does not probe this bus */
 	reg32 |= PCH_DISABLE_P2P;
 	RCBA32(FD) = reg32;
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index b628e7efe1..cbb7199b02 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -66,10 +66,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	u32 reg32;
-
 	/*
 	 *             GFX    INTA -> PIRQA (MSI)
 	 * D28IP_P3IP  WLAN   INTA -> PIRQB
@@ -108,11 +106,6 @@ void rcba_config(void)
 	RCBA16(OIC) = 0x0100;
 	/* PCH BWG says to read back the IOAPIC enable register */
 	(void) RCBA16(OIC);
-
-	/* Disable unused devices (board specific) */
-	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
-	RCBA32(FD) = reg32;
 }
 
 static uint8_t *locate_spd(void)
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 2cfefdfbab..507107a0f0 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -51,7 +51,7 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, (68 & ~3) | 0x00040001);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	u32 reg32;
 
@@ -100,7 +100,6 @@ void rcba_config(void)
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
 	/* Disable PCI bridge so MRC does not probe this bus */
 	reg32 |= PCH_DISABLE_P2P;
 	RCBA32(FD) = reg32;
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 0710f02e3d..1b02163c9b 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -57,7 +57,7 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 | 0x40001));
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	u32 reg32;
 
@@ -106,7 +106,6 @@ void rcba_config(void)
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
 	/* Disable PCI bridge so MRC does not probe this bus */
 	reg32 |= PCH_DISABLE_P2P;
 	RCBA32(FD) = reg32;
diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c
index 53b44b6c8f..0742543130 100644
--- a/src/mainboard/hp/2570p/romstage.c
+++ b/src/mainboard/hp/2570p/romstage.c
@@ -32,9 +32,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c
index 0d48f58e7f..c6d9a7c535 100644
--- a/src/mainboard/hp/2760p/romstage.c
+++ b/src/mainboard/hp/2760p/romstage.c
@@ -31,9 +31,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c
index 7d228e99cd..0aa9a1ae58 100644
--- a/src/mainboard/hp/8460p/romstage.c
+++ b/src/mainboard/hp/8460p/romstage.c
@@ -38,9 +38,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/romstage.c
index 2f48aaa6ac..bb9298ca9b 100644
--- a/src/mainboard/hp/8470p/romstage.c
+++ b/src/mainboard/hp/8470p/romstage.c
@@ -37,9 +37,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c
index dbf786eda4..c70660aee9 100644
--- a/src/mainboard/hp/revolve_810_g1/romstage.c
+++ b/src/mainboard/hp/revolve_810_g1/romstage.c
@@ -37,13 +37,11 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable devices.  */
 	RCBA32(BUC) = 0x00000000;
-	RCBA32(FD) = 0x17f21feb;
-
 }
+
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 },
 	{ 1, 0, 0 },
diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index b15f11f4de..f33415741f 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -41,10 +41,10 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	/* Disable devices */
-	RCBA32(FD) |= PCH_DISABLE_ALWAYS | PCH_DISABLE_P2P | PCH_DISABLE_XHCI;
+	RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI;
 
 #if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
 	/* Enable Gigabit Ethernet */
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 0759e6252a..3271d630c9 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -63,16 +63,9 @@ void pch_enable_lpc(void)
 	}
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	u32 reg32;
-
 	southbridge_configure_default_intmap();
-
-	/* Disable unused devices (board specific) */
-	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
-	RCBA32(FD) = reg32;
 }
 
 void mainboard_config_superio(void)
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index 799f17b1ea..2a674a5374 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -51,13 +51,12 @@ void pch_enable_lpc(void)
 			   COMA_LPC_EN | COMB_LPC_EN);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	u32 reg32;
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
 	/* Disable PCI bridge so MRC does not probe this bus */
 	reg32 |= PCH_DISABLE_P2P;
 	RCBA32(FD) = reg32;
diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c
index 84590ae5dc..0f6ffede3d 100644
--- a/src/mainboard/lenovo/l520/romstage.c
+++ b/src/mainboard/lenovo/l520/romstage.c
@@ -32,12 +32,9 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable devices.  */
 	RCBA32(0x3414) = 0x00000000;
-	RCBA32(0x3418) = 0x00000000;
-
 }
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },
diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c
index 43a3d52291..b83eeaec73 100644
--- a/src/mainboard/lenovo/s230u/romstage.c
+++ b/src/mainboard/lenovo/s230u/romstage.c
@@ -55,12 +55,10 @@ void pch_enable_lpc(void)
 		ec_mm_set_bit(0x3b, 4);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	/* Disable devices.  */
 	RCBA32(0x3414) = 0x00000020;
-	RCBA32(0x3418) = 0x17f41fe3;
-
 }
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 },
diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c
index 9f178ea741..36e83a3c72 100644
--- a/src/mainboard/lenovo/t420/romstage.c
+++ b/src/mainboard/lenovo/t420/romstage.c
@@ -60,12 +60,11 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x1ea51fe3;
 	RCBA32(BUC) = 0;
 }
+
 // OC3 set in bios to port 2-7, OC7 set in bios to port 10-13
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1,  0 }, /* P0: system port 4, OC0 */
diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c
index ad49637e2c..55011cf2e2 100644
--- a/src/mainboard/lenovo/t420s/romstage.c
+++ b/src/mainboard/lenovo/t420s/romstage.c
@@ -62,10 +62,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x1eb51fe3;
 	RCBA32(BUC) = 0;
 }
 
diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c
index eb558ac1b8..94679df0a6 100644
--- a/src/mainboard/lenovo/t430/romstage.c
+++ b/src/mainboard/lenovo/t430/romstage.c
@@ -57,11 +57,8 @@ void pch_enable_lpc(void)
 			   (0x0c << 16) | EC_LENOVO_PMH7_BASE | 1);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific, reserved only).
-	 * FIXME: Test if reserved bits are read only. */
-	RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;
 }
 
 /* FIXME: used T530 values here */
diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c
index 89ef10cd2b..3f6d9f2836 100644
--- a/src/mainboard/lenovo/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/romstage.c
@@ -36,10 +36,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x17e81fe3;
 	RCBA32(BUC) = 0;
 }
 
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index b5ea17cbac..d6e5edd92d 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -76,10 +76,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x1ee51fe3;
 	RCBA32(BUC) = 0;
 }
 
diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index cd2e0e108c..f8bb490323 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -64,10 +64,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x17f81fe3;
 	RCBA32(BUC) = 0;
 }
 
diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c
index 707848b9b3..43e0bd7dfb 100644
--- a/src/mainboard/lenovo/x131e/romstage.c
+++ b/src/mainboard/lenovo/x131e/romstage.c
@@ -33,9 +33,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x000c06a1);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	RCBA32(FD) |= PCH_DISABLE_ALWAYS;
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
index 5f7b82e81a..029d867b74 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
@@ -86,7 +86,7 @@ static uint8_t *get_spd_data(int spd_index)
 	return spd_file + spd_index * 256;
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 }
 
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index fa52778608..a6c5793359 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -47,10 +47,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x1fa41fe3;
 	RCBA32(BUC) = 0;
 }
 
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 4d8f330b2a..1a7decce59 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -50,10 +50,8 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	/* Disable unused devices (board specific) */
-	RCBA32(FD) = 0x17f81fe3;
 	RCBA32(BUC) = 0;
 }
 
diff --git a/src/mainboard/roda/rv11/romstage.c b/src/mainboard/roda/rv11/romstage.c
index 7219b0b397..b36725c213 100644
--- a/src/mainboard/roda/rv11/romstage.c
+++ b/src/mainboard/roda/rv11/romstage.c
@@ -16,13 +16,12 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	u32 reg32;
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
 	/* Disable PCI bridge so MRC does not probe this bus */
 	reg32 |= PCH_DISABLE_P2P;
 	RCBA32(FD) = reg32;
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 1fde58ef95..131be72baf 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -63,10 +63,8 @@ void pch_enable_lpc(void)
 #endif
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	u32 reg32;
-
 	/*
 	 *             GFX    INTA -> PIRQA (MSI)
 	 * D28IP_P1IP  WLAN   INTA -> PIRQB
@@ -107,11 +105,6 @@ void rcba_config(void)
 	RCBA16(OIC) = 0x0100;
 	/* PCH BWG says to read back the IOAPIC enable register */
 	(void) RCBA16(OIC);
-
-	/* Disable unused devices (board specific) */
-	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
-	RCBA32(FD) = reg32;
 }
 
 static const uint8_t *locate_spd(void)
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 830e6b6c1c..13034933f8 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -75,10 +75,8 @@ void pch_enable_lpc(void)
 #endif
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
-	u32 reg32;
-
 	/*
 	 *             GFX    INTA -> PIRQA (MSI)
 	 * D28IP_P1IP  WLAN   INTA -> PIRQB
@@ -116,11 +114,6 @@ void rcba_config(void)
 	RCBA16(OIC) = 0x0100;
 	/* PCH BWG says to read back the IOAPIC enable register */
 	(void) RCBA16(OIC);
-
-	/* Disable unused devices (board specific) */
-	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
-	RCBA32(FD) = reg32;
 }
 
 static void setup_sio_gpios(void)
diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c
index b9a0b8c801..a20a1f758b 100644
--- a/src/mainboard/sapphire/pureplatinumh61/romstage.c
+++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c
@@ -44,12 +44,10 @@ void pch_enable_lpc(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
 }
 
-void rcba_config(void)
+void mainboard_rcba_config(void)
 {
 	/* Disable devices.  */
 	RCBA32(0x3414) = 0x00000020;
-	RCBA32(0x3418) = 0x1fce1fe3;
-
 }
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 },
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 4c596539de..0426b831e7 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -110,7 +110,8 @@ void mainboard_romstage_entry(unsigned long bist)
 	post_code(0x3c);
 
 	southbridge_configure_default_intmap();
-	rcba_config();
+	southbridge_rcba_config();
+	mainboard_rcba_config();
 
 	post_code(0x3d);
 
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index dd1a58cbc3..1f56585315 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -220,7 +220,6 @@ void report_platform_info(void);
 
 #endif /* !__SMM__ */
 
-void rcba_config(void);
 void pch_enable_lpc(void);
 void mainboard_early_init(int s3resume);
 void mainboard_config_superio(void);
diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c
index eeecb5fdbe..9bd3a26e22 100644
--- a/src/southbridge/intel/bd82x6x/early_rcba.c
+++ b/src/southbridge/intel/bd82x6x/early_rcba.c
@@ -63,3 +63,9 @@ southbridge_configure_default_intmap(void)
 	/* PCH BWG says to read back the IOAPIC enable register */
 	(void) RCBA16(OIC);
 }
+
+void
+southbridge_rcba_config(void)
+{
+	RCBA32(FD) = PCH_DISABLE_ALWAYS;
+}
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 83d9d8d1dd..b094826336 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -85,6 +85,8 @@ int smbus_read_byte(unsigned device, unsigned address);
 int early_spi_read(u32 offset, u32 size, u8 *buffer);
 void early_thermal_init(void);
 void southbridge_configure_default_intmap(void);
+void southbridge_rcba_config(void);
+void mainboard_rcba_config(void);
 void early_pch_init_native(void);
 int southbridge_detect_s3_resume(void);