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soc/intel/skylake: Enable SMBus based on mainboard config 

Enable SMBus controller based on config in mainboard devicetree.cb

BUG=None
TEST= Build for Soraka, Verify that SMBus is enabled or disabled (run
lspci in OS) based on board devicetree.cb config 'SmbusEnable'.

Change-Id: I04c8bc30c03fd8dc7cc8ae239885e740b09e9bc1
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Naresh G Solanki 2017-07-12 23:01:26 +05:30 committed by Martin Roth
parent 27db0dd790
commit ff48b3b1ec
1 changed files with 3 additions and 0 deletions
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3
src/soc/intel/skylake/romstage/romstage_fsp20.c
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@ -237,6 +237,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;
/* Enable SMBus controller based on config */
m_cfg->SmbusEnable = config->SmbusEnable;
mainboard_memory_init_params(mupd);
}