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src/southbridge: change "unsigned" to "unsigned int" 

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iee2056a50a1201626fa29194afdbfc1f11094420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36333
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2019-10-23 21:46:03 -06:00 committed by Patrick Georgi
parent 5331a7cff9
commit ff744bf0ee
67 changed files with 256 additions and 256 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/southbridge/amd/amd8111/acpi.c
View File

@ -100,7 +100,7 @@ static int lsmbus_block_write(struct device *dev, uint8_t cmd, u8 bytes,
#if CONFIG(HAVE_ACPI_TABLES)
unsigned pm_base;
unsigned int pm_base;
#endif
static void acpi_init(struct device *dev)

8
src/southbridge/amd/amd8111/amd8111.c
View File

@ -21,15 +21,15 @@ void amd8111_enable(struct device *dev)
{
struct device *lpc_dev;
struct device *bus_dev;
unsigned index;
unsigned reg_old, reg;
unsigned int index;
unsigned int reg_old, reg;
/* See if we are on the bus behind the amd8111 pci bridge */
bus_dev = dev->bus->dev;
if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) &&
(bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI))
{
unsigned devfn;
unsigned int devfn;
devfn = bus_dev->path.pci.devfn + (1 << 3);
lpc_dev = pcidev_path_behind(bus_dev->bus, devfn);
index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
@ -37,7 +37,7 @@ void amd8111_enable(struct device *dev)
index = 16;
}
} else {
unsigned devfn;
unsigned int devfn;
devfn = (dev->path.pci.devfn) & ~7;
lpc_dev = pcidev_path_behind(dev->bus, devfn);
index = dev->path.pci.devfn & 7;

2
src/southbridge/amd/amd8111/amd8111.h
View File

@ -17,6 +17,6 @@
#include <device/device.h>
void amd8111_enable(struct device *dev);
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn);
#endif /* AMD8111_H */

42
src/southbridge/amd/amd8111/amd8111_smbus.h
View File

@ -29,7 +29,7 @@ static inline void smbus_delay(void)
outb(0x80, 0x80);
}
static int smbus_wait_until_ready(unsigned smbus_io_base)
static int smbus_wait_until_ready(unsigned int smbus_io_base)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
@ -48,7 +48,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
static int smbus_wait_until_done(unsigned smbus_io_base)
static int smbus_wait_until_done(unsigned int smbus_io_base)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
@ -64,10 +64,10 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned int device)
static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device)
{
unsigned global_status_register;
unsigned byte;
unsigned int global_status_register;
unsigned int byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
@ -110,10 +110,10 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned int device)
return byte;
}
static int do_smbus_send_byte(unsigned smbus_io_base, unsigned int device,
unsigned value)
static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device,
unsigned int value)
{
unsigned global_status_register;
unsigned int global_status_register;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
@ -153,11 +153,11 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned int device,
}
static int do_smbus_read_byte(unsigned smbus_io_base, unsigned int device,
static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device,
unsigned int address)
{
unsigned global_status_register;
unsigned byte;
unsigned int global_status_register;
unsigned int byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
@ -200,10 +200,10 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned int device,
return byte;
}
static int do_smbus_write_byte(unsigned smbus_io_base, unsigned int device,
static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device,
unsigned int address, unsigned char val)
{
unsigned global_status_register;
unsigned int global_status_register;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
@ -239,11 +239,11 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned int device,
return 0;
}
static int do_smbus_block_read(unsigned smbus_io_base, unsigned int device,
unsigned cmd, u8 bytes, u8 *buf)
static int do_smbus_block_read(unsigned int smbus_io_base, unsigned int device,
unsigned int cmd, u8 bytes, u8 *buf)
{
unsigned global_status_register;
unsigned i;
unsigned int global_status_register;
unsigned int i;
u8 msglen;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
@ -296,11 +296,11 @@ static int do_smbus_block_read(unsigned smbus_io_base, unsigned int device,
return i;
}
static int do_smbus_block_write(unsigned smbus_io_base, unsigned int device,
unsigned cmd, u8 bytes, const u8 *buf)
static int do_smbus_block_write(unsigned int smbus_io_base, unsigned int device,
unsigned int cmd, u8 bytes, const u8 *buf)
{
unsigned global_status_register;
unsigned i;
unsigned int global_status_register;
unsigned int i;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;

20
src/southbridge/amd/amd8111/early_ctrl.c
View File

@ -19,7 +19,7 @@
#include <southbridge/amd/common/reset.h>
#include "amd8111.h"
unsigned get_sbdn(unsigned bus)
unsigned int get_sbdn(unsigned int bus)
{
pci_devfn_t dev;
@ -34,7 +34,7 @@ unsigned get_sbdn(unsigned bus)
}
static void enable_cf9_x(unsigned sbbusn, unsigned sbdn)
static void enable_cf9_x(unsigned int sbbusn, unsigned int sbdn)
{
pci_devfn_t dev;
uint8_t byte;
@ -48,9 +48,9 @@ static void enable_cf9_x(unsigned sbbusn, unsigned sbdn)
static void enable_cf9(void)
{
unsigned sblk = get_sblk();
unsigned sbbusn = get_sbbusn(sblk);
unsigned sbdn = get_sbdn(sbbusn);
unsigned int sblk = get_sblk();
unsigned int sbbusn = get_sbbusn(sblk);
unsigned int sbdn = get_sbdn(sbbusn);
enable_cf9_x(sbbusn, sbdn);
}
@ -63,7 +63,7 @@ void do_board_reset(void)
outb(0x0e, 0x0cf9); // make sure cf9 is enabled
}
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn)
{
pci_devfn_t dev;
@ -76,7 +76,7 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
}
static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
static void soft_reset_x(unsigned int sbbusn, unsigned int sbdn)
{
pci_devfn_t dev;
@ -91,9 +91,9 @@ static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
void do_soft_reset(void)
{
unsigned sblk = get_sblk();
unsigned sbbusn = get_sbbusn(sblk);
unsigned sbdn = get_sbdn(sbbusn);
unsigned int sblk = get_sblk();
unsigned int sbbusn = get_sbbusn(sblk);
unsigned int sbdn = get_sbdn(sbbusn);
return soft_reset_x(sbbusn, sbdn);

4
src/southbridge/amd/amd8111/early_smbus.c
View File

@ -64,13 +64,13 @@ static inline int smbus_write_byte(unsigned int device, unsigned int address,
return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
}
static inline int smbus_block_read(unsigned int device, unsigned cmd, u8 bytes,
static inline int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes,
u8 *buf)
{
return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
}
static inline int smbus_block_write(unsigned int device, unsigned cmd, u8 bytes,
static inline int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
const u8 *buf)
{
return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);

8
src/southbridge/amd/amd8111/reset.c
View File

@ -21,7 +21,7 @@
#define PCI_DEV_INVALID (0xffffffffU)
static pci_devfn_t pci_io_locate_device_on_bus(unsigned pci_id, unsigned bus)
static pci_devfn_t pci_io_locate_device_on_bus(unsigned int pci_id, unsigned int bus)
{
pci_devfn_t dev, last;
dev = PCI_DEV(bus, 0, 0);
@ -41,9 +41,9 @@ static pci_devfn_t pci_io_locate_device_on_bus(unsigned pci_id, unsigned bus)
void do_board_reset(void)
{
pci_devfn_t dev;
unsigned bus;
unsigned node = 0;
unsigned link = get_sblk();
unsigned int bus;
unsigned int node = 0;
unsigned int link = get_sblk();
/* Find the device.
* There can only be one 8111 on a hypertransport chain/bus.

20
src/southbridge/amd/amd8132/bridge.c
View File

@ -43,8 +43,8 @@ static void amd8132_walk_children(struct bus *bus,
}
struct amd8132_bus_info {
unsigned sstatus;
unsigned rev;
unsigned int sstatus;
unsigned int rev;
int master_devices;
int max_func;
};
@ -65,9 +65,9 @@ static void amd8132_count_dev(struct device *dev, void *ptr)
static void amd8132_pcix_tune_dev(struct device *dev, void *ptr)
{
struct amd8132_bus_info *info = ptr;
unsigned cap;
unsigned status, cmd, orig_cmd;
unsigned max_read, max_tran;
unsigned int cap;
unsigned int status, cmd, orig_cmd;
unsigned int max_read, max_tran;
int sibs;
if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) {
@ -133,10 +133,10 @@ static void amd8132_pcix_tune_dev(struct device *dev, void *ptr)
}
static void amd8132_scan_bus(struct bus *bus,
unsigned min_devfn, unsigned max_devfn)
unsigned int min_devfn, unsigned int max_devfn)
{
struct amd8132_bus_info info;
unsigned pos;
unsigned int pos;
/* Find the children on the bus */
pci_scan_bus(bus, min_devfn, max_devfn);
@ -162,7 +162,7 @@ static void amd8132_scan_bus(struct bus *bus,
*/
if (!bus->children)
{
unsigned pcix_misc;
unsigned int pcix_misc;
/* Disable all of my children */
disable_children(bus);
@ -198,7 +198,7 @@ static void amd8132_pcix_init(struct device *dev)
{
uint32_t dword;
uint8_t byte;
unsigned chip_rev;
unsigned int chip_rev;
/* Find the revision of the 8132 */
chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
@ -368,7 +368,7 @@ static void ioapic_enable(struct device *dev)
static void amd8132_ioapic_init(struct device *dev)
{
uint32_t dword;
unsigned chip_rev;
unsigned int chip_rev;
/* Find the revision of the 8132 */
chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);

8
src/southbridge/broadcom/bcm5785/bcm5785.c
View File

@ -31,21 +31,21 @@ void bcm5785_enable(struct device *dev)
if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
(bus_dev->device == 0x0036)) // device under PCI-X Bridge
{
unsigned devfn;
unsigned int devfn;
devfn = bus_dev->path.pci.devfn + (1 << 3);
sb_pci_main_dev = pcidev_path_behind(bus_dev->bus, devfn);
// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
} else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
(bus_dev->device == 0x0104)) // device under PCI Bridge (under PCI-X)
{
unsigned devfn;
unsigned int devfn;
devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3);
sb_pci_main_dev = pcidev_path_behind(bus_dev->bus->dev->bus,
devfn);
// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
}
else { // same bus
unsigned devfn;
unsigned int devfn;
devfn = (dev->path.pci.devfn) & ~7;
if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS) {
if (dev->device == 0x0036) //PCI-X Bridge
@ -62,7 +62,7 @@ void bcm5785_enable(struct device *dev)
// get index now
#if 0
unsigned reg_old, reg;
unsigned int reg_old, reg;
if (index < 16) {
reg = reg_old = pci_read_config16(sb_pci_main_dev, 0x48);
reg &= ~(1 << index);

2
src/southbridge/broadcom/bcm5785/bcm5785.h
View File

@ -21,7 +21,7 @@
#include "chip.h"
void bcm5785_enable(struct device *dev);
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn);
void bcm5785_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device);

4
src/southbridge/broadcom/bcm5785/early_setup.c
View File

@ -64,7 +64,7 @@ static void bcm5785_enable_wdt_port_cf9(void)
pci_write_config8(dev, 0x40, 1 << 2);
}
unsigned get_sbdn(unsigned bus)
unsigned int get_sbdn(unsigned int bus)
{
pci_devfn_t dev;
@ -81,7 +81,7 @@ unsigned get_sbdn(unsigned bus)
#define SB_VFSMAF 0
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn)
{
//ACPI Decode Enable
outb(0x0e, 0xcd6);

8
src/southbridge/broadcom/bcm5785/early_smbus.c
View File

@ -40,22 +40,22 @@ static void enable_smbus(void)
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
}
static inline int smbus_recv_byte(unsigned device)
static inline int smbus_recv_byte(unsigned int device)
{
return do_smbus_recv_byte(SMBUS_IO_BASE, device);
}
static inline int smbus_send_byte(unsigned device, unsigned char val)
static inline int smbus_send_byte(unsigned int device, unsigned char val)
{
return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
}
static inline int smbus_read_byte(unsigned device, unsigned address)
static inline int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
static inline int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val)
{
return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
}

8
src/southbridge/broadcom/bcm5785/sb_pci_main.c
View File

@ -72,7 +72,7 @@ static void bcm5785_sb_read_resources(struct device *dev)
static int lsmbus_recv_byte(struct device *dev)
{
unsigned device;
unsigned int device;
struct resource *res;
struct bus *pbus;
@ -86,7 +86,7 @@ static int lsmbus_recv_byte(struct device *dev)
static int lsmbus_send_byte(struct device *dev, uint8_t val)
{
unsigned device;
unsigned int device;
struct resource *res;
struct bus *pbus;
@ -100,7 +100,7 @@ static int lsmbus_send_byte(struct device *dev, uint8_t val)
static int lsmbus_read_byte(struct device *dev, uint8_t address)
{
unsigned device;
unsigned int device;
struct resource *res;
struct bus *pbus;
@ -114,7 +114,7 @@ static int lsmbus_read_byte(struct device *dev, uint8_t address)
static int lsmbus_write_byte(struct device *dev, uint8_t address, uint8_t val)
{
unsigned device;
unsigned int device;
struct resource *res;
struct bus *pbus;

12
src/southbridge/broadcom/bcm5785/smbus.h
View File

@ -42,7 +42,7 @@ static inline void smbus_delay(void)
outb(0x80, 0x80);
}
static int smbus_wait_until_ready(unsigned smbus_io_base)
static int smbus_wait_until_ready(unsigned int smbus_io_base)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
@ -58,7 +58,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
return -2; // time out
}
static int smbus_wait_until_done(unsigned smbus_io_base)
static int smbus_wait_until_done(unsigned int smbus_io_base)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
@ -78,7 +78,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
return -3; // timeout
}
static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device)
{
uint8_t byte;
@ -105,7 +105,7 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
return byte;
}
static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)
static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device, unsigned char val)
{
uint8_t byte;
@ -132,7 +132,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned
return 0;
}
static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address)
{
uint8_t byte;
@ -162,7 +162,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
return byte;
}
static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address, unsigned char val)
{
uint8_t byte;

2
src/southbridge/intel/bd82x6x/early_smbus.c
View File

@ -51,7 +51,7 @@ void enable_smbus(void)
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
int smbus_read_byte(unsigned device, unsigned address)
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}

8
src/southbridge/intel/bd82x6x/me.c
View File

@ -154,7 +154,7 @@ static inline u32 read_cb(void)
static int mei_wait_for_me_ready(void)
{
struct mei_csr me;
unsigned try = ME_RETRY;
unsigned int try = ME_RETRY;
while (try--) {
read_me_csr(&me);
@ -195,7 +195,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi,
void *req_data)
{
struct mei_csr host;
unsigned ndata, n;
unsigned int ndata, n;
u32 *data;
/* Number of dwords to write, ignoring MKHI */
@ -260,8 +260,8 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi,
struct mei_header mei_rsp;
struct mkhi_header mkhi_rsp;
struct mei_csr me, host;
unsigned ndata, n;
unsigned expected;
unsigned int ndata, n;
unsigned int expected;
u32 *data;
/* Total number of dwords to read from circular buffer */

8
src/southbridge/intel/bd82x6x/me_8.x.c
View File

@ -156,7 +156,7 @@ static inline u32 read_cb(void)
static int mei_wait_for_me_ready(void)
{
struct mei_csr me;
unsigned try = ME_RETRY;
unsigned int try = ME_RETRY;
while (try--) {
read_me_csr(&me);
@ -197,7 +197,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi,
void *req_data)
{
struct mei_csr host;
unsigned ndata, n;
unsigned int ndata, n;
u32 *data;
/* Number of dwords to write, ignoring MKHI */
@ -262,8 +262,8 @@ static int mei_recv_msg(struct mkhi_header *mkhi,
struct mei_header mei_rsp;
struct mkhi_header mkhi_rsp;
struct mei_csr me, host;
unsigned ndata, n/*, me_data_len*/;
unsigned expected;
unsigned int ndata, n/*, me_data_len*/;
unsigned int expected;
u32 *data;
/* Total number of dwords to read from circular buffer */

4
src/southbridge/intel/bd82x6x/pch.c
View File

@ -87,7 +87,7 @@ int pch_silicon_supported(int type, int rev)
#define IOBP_RETRY 1000
static inline int iobp_poll(void)
{
unsigned try = IOBP_RETRY;
unsigned int try = IOBP_RETRY;
u32 data;
while (try--) {
@ -147,7 +147,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
#ifndef __SMM__
/* Set bit in function disable register to hide this device */
static void pch_hide_devfn(unsigned devfn)
static void pch_hide_devfn(unsigned int devfn)
{
switch (devfn) {
case PCI_DEVFN(20, 0): /* xHCI */

2
src/southbridge/intel/bd82x6x/pch.h
View File

@ -66,7 +66,7 @@ void enable_smbus(void);
void enable_usb_bar(void);
#if ENV_ROMSTAGE
int smbus_read_byte(unsigned device, unsigned address);
int smbus_read_byte(unsigned int device, unsigned int address);
#endif
void early_thermal_init(void);

4
src/southbridge/intel/bd82x6x/usb_ehci.c
View File

@ -74,8 +74,8 @@ static void usb_ehci_init(struct device *dev)
printk(BIOS_DEBUG, "done.\n");
}
static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
u8 access_cntl;

6
src/southbridge/intel/common/gpio.c
View File

@ -124,11 +124,11 @@ int get_gpio(int gpio_num)
* get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.
*/
unsigned get_gpios(const int *gpio_num_array)
unsigned int get_gpios(const int *gpio_num_array)
{
int gpio;
unsigned bitmask = 1;
unsigned vector = 0;
unsigned int bitmask = 1;
unsigned int vector = 0;
while (bitmask &&
((gpio = *gpio_num_array++) != -1)) {

2
src/southbridge/intel/common/gpio.h
View File

@ -172,7 +172,7 @@ int get_gpio(int gpio_num);
* get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.
*/
unsigned get_gpios(const int *gpio_num_array);
unsigned int get_gpios(const int *gpio_num_array);
void set_gpio(int gpio_num, int value);

26
src/southbridge/intel/common/spi.c
View File

@ -102,7 +102,7 @@ struct ich_spi_controller {
uint16_t *optype;
uint32_t *addr;
uint8_t *data;
unsigned databytes;
unsigned int databytes;
uint8_t *status;
uint16_t *control;
uint32_t *bbar;
@ -169,7 +169,7 @@ static u8 readb_(const void *addr)
u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@ -178,7 +178,7 @@ static u16 readw_(const void *addr)
u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@ -187,7 +187,7 @@ static u32 readl_(const void *addr)
u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@ -195,21 +195,21 @@ static void writeb_(u8 b, void *addr)
{
write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, void *addr)
{
write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, void *addr)
{
write32(addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
b, ((unsigned int) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
@ -367,13 +367,13 @@ typedef struct spi_transaction {
uint32_t offset;
} spi_transaction;
static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
{
trans->out += bytes;
trans->bytesout -= bytes;
}
static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
{
trans->in += bytes;
trans->bytesin -= bytes;
@ -801,8 +801,8 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
if (addr + len > flash->size) {
printk(BIOS_ERR,
"Attempt to read %x-%x which is out of chip\n",
(unsigned) addr,
(unsigned) addr+(unsigned) len);
(unsigned int) addr,
(unsigned int) addr+(unsigned int) len);
return -1;
}
@ -872,7 +872,7 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
if (addr + len > flash->size) {
printk(BIOS_ERR,
"Attempt to write 0x%x-0x%x which is out of chip\n",
(unsigned)addr, (unsigned) (addr+len));
(unsigned int)addr, (unsigned int) (addr+len));
return -1;
}
@ -906,7 +906,7 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
len -= block_len;
}
printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
(unsigned) (addr - start), start);
(unsigned int) (addr - start), start);
return 0;
}

2
src/southbridge/intel/fsp_rangeley/early_smbus.c
View File

@ -51,7 +51,7 @@ void enable_smbus(void)
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
int smbus_read_byte(unsigned device, unsigned address)
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}

2
src/southbridge/intel/fsp_rangeley/gpio.h
View File

@ -119,6 +119,6 @@ int get_gpio(int gpio_num);
* Get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of GPIO pin numbers to scan, terminated by -1.
*/
unsigned get_gpios(const int *gpio_num_array);
unsigned int get_gpios(const int *gpio_num_array);
#endif

2
src/southbridge/intel/fsp_rangeley/soc.c
View File

@ -59,7 +59,7 @@ int soc_silicon_supported(int type, int rev)
}
/* Set bit in Function Disable register to hide this device */
static void soc_hide_devfn(unsigned devfn)
static void soc_hide_devfn(unsigned int devfn)
{
/* TODO Function Disable. */
}

18
src/southbridge/intel/fsp_rangeley/spi.c
View File

@ -121,7 +121,7 @@ typedef struct ich_spi_controller {
uint16_t *optype;
uint32_t *addr;
uint8_t *data;
unsigned databytes;
unsigned int databytes;
uint8_t *status;
uint16_t *control;
uint32_t *bbar;
@ -199,7 +199,7 @@ static u8 readb_(const void *addr)
{
u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@ -207,7 +207,7 @@ static u16 readw_(const void *addr)
{
u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@ -215,7 +215,7 @@ static u32 readl_(const void *addr)
{
u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
v, ((unsigned int) addr & 0xffff) - 0xf020);
return v;
}
@ -223,21 +223,21 @@ static void writeb_(u8 b, const void *addr)
{
write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
b, ((unsigned int) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
write32((unsigned long)addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
b, ((unsigned int) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
@ -397,13 +397,13 @@ typedef struct spi_transaction {
uint32_t offset;
} spi_transaction;
static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
{
trans->out += bytes;
trans->bytesout -= bytes;
}
static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
{
trans->in += bytes;
trans->bytesin -= bytes;

2
src/southbridge/intel/i82801dx/i82801dx.h
View File

@ -36,7 +36,7 @@
void i82801dx_enable(struct device *dev);
void enable_smbus(void);
int smbus_read_byte(unsigned device, unsigned address);
int smbus_read_byte(unsigned int device, unsigned int address);
void aseg_smm_lock(void);
#endif

2
src/southbridge/intel/i82801ix/early_smbus.c
View File

@ -52,7 +52,7 @@ void enable_smbus(void)
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
int smbus_read_byte(unsigned device, unsigned address)
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}

2
src/southbridge/intel/i82801ix/i82801ix.c
View File

@ -137,7 +137,7 @@ static void i82801ix_ehci_init(void)
(1 << 29) | (1 << 17) | (2 << 2));
}
static int i82801ix_function_disabled(const unsigned devfn)
static int i82801ix_function_disabled(const unsigned int devfn)
{
struct device *const dev = pcidev_path_on_root(devfn);
if (!dev) {

2
src/southbridge/intel/i82801ix/i82801ix.h
View File

@ -215,7 +215,7 @@ void i82801ix_dmi_setup(void);
void i82801ix_dmi_poll_vc1(void);
#if ENV_ROMSTAGE
int smbus_read_byte(unsigned device, unsigned address);
int smbus_read_byte(unsigned int device, unsigned int address);
#endif
#endif

4
src/southbridge/intel/i82801ix/usb_ehci.c
View File

@ -34,8 +34,8 @@ static void usb_ehci_init(struct device *dev)
printk(BIOS_DEBUG, "done.\n");
}
static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
u8 access_cntl;

2
src/southbridge/intel/i82801jx/early_smbus.c
View File

@ -47,7 +47,7 @@ void enable_smbus(void)
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
int smbus_read_byte(unsigned device, unsigned address)
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}

2
src/southbridge/intel/i82801jx/i82801jx.h
View File

@ -227,7 +227,7 @@ static inline int lpc_is_mobile(const u16 devid)
#if ENV_ROMSTAGE
void enable_smbus(void);
int smbus_read_byte(unsigned device, unsigned address);
int smbus_read_byte(unsigned int device, unsigned int address);
int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
u8 *buf);
int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);

4
src/southbridge/intel/i82801jx/usb_ehci.c
View File

@ -34,8 +34,8 @@ static void usb_ehci_init(struct device *dev)
printk(BIOS_DEBUG, "done.\n");
}
static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
u8 access_cntl;

8
src/southbridge/intel/ibexpeak/early_smbus.c
View File

@ -51,22 +51,22 @@ void enable_smbus(void)
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
int smbus_read_byte(unsigned device, unsigned address)
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
int smbus_write_byte(unsigned device, unsigned address, u8 data)
int smbus_write_byte(unsigned int device, unsigned int address, u8 data)
{
return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data);
}
int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf)
int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf)
{
return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
}
int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf)
int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf)
{
return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
}

8
src/southbridge/intel/ibexpeak/me.c
View File

@ -155,7 +155,7 @@ static inline u32 read_cb(void)
static int mei_wait_for_me_ready(void)
{
struct mei_csr me;
unsigned try = ME_RETRY;
unsigned int try = ME_RETRY;
while (try--) {
read_me_csr(&me);
@ -196,7 +196,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi,
void *req_data)
{
struct mei_csr host;
unsigned ndata, n;
unsigned int ndata, n;
u32 *data;
/* Number of dwords to write, ignoring MKHI */
@ -261,8 +261,8 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi,
struct mei_header mei_rsp;
struct mkhi_header mkhi_rsp;
struct mei_csr me, host;
unsigned ndata, n;
unsigned expected;
unsigned int ndata, n;
unsigned int expected;
u32 *data;
/* Total number of dwords to read from circular buffer */

8
src/southbridge/intel/ibexpeak/pch.h
View File

@ -56,10 +56,10 @@ void enable_smbus(void);
void enable_usb_bar(void);
#if ENV_ROMSTAGE
int smbus_read_byte(unsigned device, unsigned address);
int smbus_write_byte(unsigned device, unsigned address, u8 data);
int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf);
int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf);
int smbus_read_byte(unsigned int device, unsigned int address);
int smbus_write_byte(unsigned int device, unsigned int address, u8 data);
int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf);
#endif
void early_pch_init(void);

4
src/southbridge/intel/ibexpeak/usb_ehci.c
View File

@ -68,8 +68,8 @@ static void usb_ehci_init(struct device *dev)
printk(BIOS_DEBUG, "done.\n");
}
static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
u8 access_cntl;

2
src/southbridge/intel/lynxpoint/early_smbus.c
View File

@ -51,7 +51,7 @@ void enable_smbus(void)
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
int smbus_read_byte(unsigned device, unsigned address)
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}

6
src/southbridge/intel/lynxpoint/lp_gpio.c
View File

@ -127,11 +127,11 @@ int get_gpio(int gpio_num)
* get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.
*/
unsigned get_gpios(const int *gpio_num_array)
unsigned int get_gpios(const int *gpio_num_array)
{
int gpio;
unsigned bitmask = 1;
unsigned vector = 0;
unsigned int bitmask = 1;
unsigned int vector = 0;
while (bitmask &&
((gpio = *gpio_num_array++) != -1)) {

2
src/southbridge/intel/lynxpoint/lp_gpio.h
View File

@ -169,7 +169,7 @@ int get_gpio(int gpio_num);
* get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.
*/
unsigned get_gpios(const int *gpio_num_array);
unsigned int get_gpios(const int *gpio_num_array);
void set_gpio(int gpio_num, int value);

8
src/southbridge/intel/lynxpoint/me_9.x.c
View File

@ -162,7 +162,7 @@ static inline u32 read_cb(void)
static int mei_wait_for_me_ready(void)
{
struct mei_csr me;
unsigned try = ME_RETRY;
unsigned int try = ME_RETRY;
while (try--) {
read_me_csr(&me);
@ -202,7 +202,7 @@ static void mei_reset(void)
static int mei_send_packet(struct mei_header *mei, void *req_data)
{
struct mei_csr host;
unsigned ndata, n;
unsigned int ndata, n;
u32 *data;
/* Number of dwords to write */
@ -306,8 +306,8 @@ static int mei_recv_msg(void *header, int header_bytes,
{
struct mei_header mei_rsp;
struct mei_csr me, host;
unsigned ndata, n;
unsigned expected;
unsigned int ndata, n;
unsigned int expected;
u32 *data;
/* Total number of dwords to read from circular buffer */

2
src/southbridge/intel/lynxpoint/pch.c
View File

@ -197,7 +197,7 @@ void pch_disable_devfn(struct device *dev)
#define IOBP_RETRY 1000
static inline int iobp_poll(void)
{
unsigned try;
unsigned int try;
for (try = IOBP_RETRY; try > 0; try--) {
u16 status = RCBA16(IOBPS);

2
src/southbridge/intel/lynxpoint/pch.h
View File

@ -177,7 +177,7 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
void enable_smbus(void);
#if ENV_ROMSTAGE
int smbus_read_byte(unsigned device, unsigned address);
int smbus_read_byte(unsigned int device, unsigned int address);
#endif
void enable_usb_bar(void);

2
src/southbridge/intel/lynxpoint/pcie.c
View File

@ -168,7 +168,7 @@ static void root_port_init_config(struct device *dev)
static void pch_pcie_device_set_func(int index, int pci_func)
{
struct device *dev;
unsigned new_devfn;
unsigned int new_devfn;
dev = rpc.ports[index];

8
src/southbridge/nvidia/ck804/ck804.c
View File

@ -22,7 +22,7 @@
static u32 final_reg;
static struct device *find_lpc_dev(struct device *dev, unsigned devfn)
static struct device *find_lpc_dev(struct device *dev, unsigned int devfn)
{
struct device *lpc_dev;
@ -54,7 +54,7 @@ static struct device *find_lpc_dev(struct device *dev, unsigned devfn)
static void ck804_enable(struct device *dev)
{
struct device *lpc_dev;
unsigned index = 0, index2 = 0, deviceid, vendorid, devfn;
unsigned int index = 0, index2 = 0, deviceid, vendorid, devfn;
u32 reg_old, reg;
u8 byte;
@ -179,8 +179,8 @@ static void ck804_enable(struct device *dev)
}
}
static void ck804_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
static void ck804_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));

2
src/southbridge/nvidia/ck804/ck804.h
View File

@ -26,6 +26,6 @@
#define CK804B_BUSN 0x80
#define CK804B_DEVN_BASE (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) ? CK804_DEVN_BASE : 1)
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn);
#endif

26
src/southbridge/nvidia/ck804/early_setup_car.c
View File

@ -24,20 +24,20 @@
#include "ck804.h"
/* Someone messed up and snuck in some K8-specific code */
static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val) { return 0; /* stub */};
static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned int vendorid, unsigned int val) { return 0; /* stub */};
static int set_ht_link_ck804(u8 ht_c_num)
{
unsigned vendorid = 0x10de;
unsigned val = 0x01610169;
unsigned int vendorid = 0x10de;
unsigned int val = 0x01610169;
return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
}
static void setup_ss_table(unsigned index, unsigned where, unsigned control,
static void setup_ss_table(unsigned int index, unsigned int where, unsigned int control,
const unsigned int *register_values, int max)
{
int i;
unsigned val;
unsigned int val;
val = inl(control);
val &= 0xfffffffe;
@ -77,8 +77,8 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
*/
#define CK804_DEV(d, f, r) PCI_ADDR(0, d, f, r)
static void ck804_early_set_port(unsigned ck804_num, unsigned *busn,
unsigned *io_base)
static void ck804_early_set_port(unsigned int ck804_num, unsigned int *busn,
unsigned int *io_base)
{
static const unsigned int ctrl_devport_conf[] = {
CK804_DEV(0x1, 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
@ -97,8 +97,8 @@ static void ck804_early_set_port(unsigned ck804_num, unsigned *busn,
}
}
static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn,
unsigned *io_base)
static void ck804_early_clear_port(unsigned int ck804_num, unsigned int *busn,
unsigned int *io_base)
{
static const unsigned int ctrl_devport_conf_clear[] = {
CK804_DEV(0x1, 0, ANACTRL_REG_POS), ~(0x0000ff01), 0,
@ -117,8 +117,8 @@ static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn,
}
}
static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
unsigned *io_base)
static void ck804_early_setup(unsigned int ck804_num, unsigned int *busn,
unsigned int *io_base)
{
static const unsigned int ctrl_conf_master[] = {
RES_PCI_IO, CK804_DEV(1, 2, 0x8c), 0xffff0000, 0x00009880,
@ -337,7 +337,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
static int ck804_early_setup_x(void)
{
unsigned busn[4], io_base[4];
unsigned int busn[4], io_base[4];
int i, ck804_num = 0;
for (i = 0; i < 4; i++) {
@ -380,7 +380,7 @@ void do_soft_reset(void)
outb(0x06, 0x0cf9);
}
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn)
{
/* The default value for CK804 is good. */
/* Set VFSMAF (VID/FID System Management Action Field) to 2. */

8
src/southbridge/nvidia/ck804/early_smbus.c
View File

@ -55,23 +55,23 @@ void enable_smbus(void)
printk(BIOS_DEBUG, "SMBus controller enabled\n");
}
int ck804_smbus_read_byte(unsigned bus, unsigned device, unsigned address)
int ck804_smbus_read_byte(unsigned int bus, unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_BASE(bus), device, address);
}
int ck804_smbus_write_byte(unsigned bus, unsigned device, unsigned address,
int ck804_smbus_write_byte(unsigned int bus, unsigned int device, unsigned int address,
unsigned char val)
{
return do_smbus_write_byte(SMBUS_BASE(bus), device, address, val);
}
int smbus_read_byte(unsigned device, unsigned address)
int smbus_read_byte(unsigned int device, unsigned int address)
{
return ck804_smbus_read_byte(0, device, address);
}
int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val)
{
return ck804_smbus_write_byte(0, device, address, val);
}

2
src/southbridge/nvidia/ck804/early_smbus.h
View File

@ -11,7 +11,7 @@
* GNU General Public License for more details.
*/
int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned);
int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned int);
int ck804_smbus_write_byte(unsigned int, unsigned int, unsigned int, unsigned char);
void enable_smbus(void);
int smbus_read_byte(unsigned int, unsigned int);

2
src/southbridge/nvidia/ck804/fadt.c
View File

@ -22,7 +22,7 @@
#include <arch/acpi.h>
#include <version.h>
extern unsigned pm_base; /* pm_base should be set in sb acpi */
extern unsigned int pm_base; /* pm_base should be set in sb acpi */
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{

2
src/southbridge/nvidia/ck804/lpc.c
View File

@ -97,7 +97,7 @@ static void rom_dummy_write(struct device *dev)
pci_write_config8(dev, 0x6d, new);
}
unsigned pm_base = 0;
unsigned int pm_base = 0;
static void lpc_init(struct device *dev)
{

2
src/southbridge/nvidia/ck804/sata.c
View File

@ -27,7 +27,7 @@
#endif
#if CK804_SATA_RESET_FOR_ATAPI
static void sata_com_reset(struct device *dev, unsigned reset)
static void sata_com_reset(struct device *dev, unsigned int reset)
// reset = 1 : reset
// reset = 0 : clear
{

8
src/southbridge/nvidia/ck804/smbus.c
View File

@ -23,7 +23,7 @@
static int lsmbus_recv_byte(struct device *dev)
{
unsigned device;
unsigned int device;
struct resource *res;
struct bus *pbus;
@ -37,7 +37,7 @@ static int lsmbus_recv_byte(struct device *dev)
static int lsmbus_send_byte(struct device *dev, u8 val)
{
unsigned device;
unsigned int device;
struct resource *res;
struct bus *pbus;
@ -51,7 +51,7 @@ static int lsmbus_send_byte(struct device *dev, u8 val)
static int lsmbus_read_byte(struct device *dev, u8 address)
{
unsigned device;
unsigned int device;
struct resource *res;
struct bus *pbus;
@ -65,7 +65,7 @@ static int lsmbus_read_byte(struct device *dev, u8 address)
static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
{
unsigned device;
unsigned int device;
struct resource *res;
struct bus *pbus;

18
src/southbridge/nvidia/ck804/smbus.h
View File

@ -35,7 +35,7 @@ static inline void smbus_delay(void)
outb(0x80, 0x80);
}
static int smbus_wait_until_done(unsigned smbus_io_base)
static int smbus_wait_until_done(unsigned int smbus_io_base)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
@ -52,7 +52,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
/* Platform has severe issues placing non-inlined functions in headers. */
#if ENV_RAMSTAGE
static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device)
{
unsigned char global_status_register, byte;
@ -85,10 +85,10 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
return byte;
}
static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device,
static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device,
unsigned char val)
{
unsigned global_status_register;
unsigned int global_status_register;
outb(val, smbus_io_base + SMBHSTDAT0);
smbus_delay();
@ -118,8 +118,8 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device,
}
#endif /* ENV_RAMSTAGE */
static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device,
unsigned address)
static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device,
unsigned int address)
{
unsigned char global_status_register, byte;
@ -152,10 +152,10 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device,
return byte;
}
static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device,
unsigned address, unsigned char val)
static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device,
unsigned int address, unsigned char val)
{
unsigned global_status_register;
unsigned int global_status_register;
outb(val, smbus_io_base + SMBHSTDAT0);
smbus_delay();

2
src/southbridge/nvidia/mcp55/early_ctrl.c
View File

@ -38,7 +38,7 @@ void do_board_reset(void)
outb(0x0e, 0x0cf9);
}
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn)
{
/* The default value for MCP55 is good. */
/* Set VFSMAF (VID/FID System Management Action Field) to 2. */

38
src/southbridge/nvidia/mcp55/early_setup_car.c
View File

@ -21,21 +21,21 @@
#include <device/pci_ops.h>
#ifdef UNUSED_CODE
int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val);
int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned int vendorid, unsigned int val);
static int set_ht_link_mcp55(u8 ht_c_num)
{
unsigned vendorid = 0x10de;
unsigned val = 0x01610109;
unsigned int vendorid = 0x10de;
unsigned int val = 0x01610109;
/* NVIDIA MCP55 hardcode, hardware can not set it automatically. */
return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
}
static void setup_ss_table(unsigned index, unsigned where, unsigned control,
static void setup_ss_table(unsigned int index, unsigned int where, unsigned int control,
const unsigned int *register_values, int max)
{
int i;
unsigned val;
unsigned int val;
val = inl(control);
val &= 0xfffffffe;
@ -82,8 +82,8 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
*/
#define MCP55_DEV(d, f, r) PCI_ADDR(0, d, f, r)
static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn,
unsigned *devn, unsigned *io_base)
static void mcp55_early_set_port(unsigned int mcp55_num, unsigned int *busn,
unsigned int *devn, unsigned int *io_base)
{
static const unsigned int ctrl_devport_conf[] = {
@ -100,8 +100,8 @@ static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn,
}
}
static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn,
unsigned *devn, unsigned *io_base)
static void mcp55_early_clear_port(unsigned int mcp55_num, unsigned int *busn,
unsigned int *devn, unsigned int *io_base)
{
static const unsigned int ctrl_devport_conf_clear[] = {
MCP55_DEV(1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0,
@ -117,8 +117,8 @@ static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn,
}
}
static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx,
unsigned anactrl_io_base, unsigned pci_e_x)
static void mcp55_early_pcie_setup(unsigned int busnx, unsigned int devnx,
unsigned int anactrl_io_base, unsigned int pci_e_x)
{
u32 tgio_ctrl, pll_ctrl, dword;
int i;
@ -156,9 +156,9 @@ static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx,
mdelay(100); /* Need to wait 100ms. */
}
static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
unsigned *devn, unsigned *io_base,
unsigned *pci_e_x)
static void mcp55_early_setup(unsigned int mcp55_num, unsigned int *busn,
unsigned int *devn, unsigned int *io_base,
unsigned int *pci_e_x)
{
static const unsigned int ctrl_conf_1[] = {
RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000,
@ -348,21 +348,21 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
static int mcp55_early_setup_x(void)
{
/* Find out how many MCP55 we have. */
unsigned busn[HT_CHAIN_NUM_MAX] = {0};
unsigned devn[HT_CHAIN_NUM_MAX] = {0};
unsigned io_base[HT_CHAIN_NUM_MAX] = {0};
unsigned int busn[HT_CHAIN_NUM_MAX] = {0};
unsigned int devn[HT_CHAIN_NUM_MAX] = {0};
unsigned int io_base[HT_CHAIN_NUM_MAX] = {0};
/*
* FIXME: May have problem if there is different MCP55 HTX card with
* different PCI_E lane allocation. Need to use same trick about
* pci1234 to verify node/link connection.
*/
unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {
unsigned int pci_e_x[HT_CHAIN_NUM_MAX] = {
CONFIG_MCP55_PCI_E_X_0, CONFIG_MCP55_PCI_E_X_1,
CONFIG_MCP55_PCI_E_X_2, CONFIG_MCP55_PCI_E_X_3,
};
int mcp55_num = 0, ht_c_index;
unsigned busnx, devnx;
unsigned int busnx, devnx;
/* FIXME: Multi PCI segment handling. */

20
src/southbridge/nvidia/mcp55/early_smbus.c
View File

@ -48,48 +48,48 @@ void enable_smbus(void)
outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT);
}
int smbus_recv_byte(unsigned device)
int smbus_recv_byte(unsigned int device)
{
return do_smbus_recv_byte(SMBUS0_IO_BASE, device);
}
int smbus_send_byte(unsigned device, unsigned char val)
int smbus_send_byte(unsigned int device, unsigned char val)
{
return do_smbus_send_byte(SMBUS0_IO_BASE, device, val);
}
int smbus_read_byte(unsigned device, unsigned address)
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS0_IO_BASE, device, address);
}
int smbus_write_byte(unsigned device, unsigned address,
int smbus_write_byte(unsigned int device, unsigned int address,
unsigned char val)
{
return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val);
}
int smbusx_recv_byte(unsigned smb_index, unsigned device)
int smbusx_recv_byte(unsigned int smb_index, unsigned int device)
{
return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index << 8), device);
}
int smbusx_send_byte(unsigned smb_index, unsigned device,
int smbusx_send_byte(unsigned int smb_index, unsigned int device,
unsigned char val)
{
return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index << 8),
device, val);
}
int smbusx_read_byte(unsigned smb_index, unsigned device,
unsigned address)
int smbusx_read_byte(unsigned int smb_index, unsigned int device,
unsigned int address)
{
return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index << 8),
device, address);
}
int smbusx_write_byte(unsigned smb_index, unsigned device,
unsigned address, unsigned char val)
int smbusx_write_byte(unsigned int smb_index, unsigned int device,
unsigned int address, unsigned char val)
{
return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index << 8),
device, address, val);

2
src/southbridge/nvidia/mcp55/fadt.c
View File

@ -23,7 +23,7 @@
#include <device/pci_ids.h>
#include <version.h>
extern unsigned pm_base;
extern unsigned int pm_base;
/* Create the Fixed ACPI Description Tables (FADT) for this board. */
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)

10
src/southbridge/nvidia/mcp55/mcp55.c
View File

@ -25,7 +25,7 @@
static u32 final_reg;
static struct device *find_lpc_dev(struct device *dev, unsigned devfn)
static struct device *find_lpc_dev(struct device *dev, unsigned int devfn)
{
struct device *lpc_dev;
@ -55,10 +55,10 @@ static struct device *find_lpc_dev(struct device *dev, unsigned devfn)
void mcp55_enable(struct device *dev)
{
struct device *lpc_dev = NULL, *sm_dev = NULL;
unsigned index = 0, index2 = 0;
unsigned int index = 0, index2 = 0;
u32 reg_old, reg;
u8 byte;
unsigned deviceid, vendorid, devfn;
unsigned int deviceid, vendorid, devfn;
int i;
if (dev->device == 0x0000) {
@ -217,8 +217,8 @@ void mcp55_enable(struct device *dev)
}
}
static void mcp55_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
static void mcp55_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));

18
src/southbridge/nvidia/mcp55/mcp55.h
View File

@ -30,19 +30,19 @@ void mcp55_enable(struct device *dev);
extern struct pci_operations mcp55_pci_ops;
#endif
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn);
void enable_smbus(void);
/* Concflict declarations with <device/smbus.h>. */
#if !ENV_RAMSTAGE
int smbus_recv_byte(unsigned device);
int smbus_send_byte(unsigned device, unsigned char val);
int smbus_read_byte(unsigned device, unsigned address);
int smbus_write_byte(unsigned device, unsigned address, unsigned char val);
int smbusx_recv_byte(unsigned smb_index, unsigned device);
int smbusx_send_byte(unsigned smb_index, unsigned device, unsigned char val);
int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address);
int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address,
int smbus_recv_byte(unsigned int device);
int smbus_send_byte(unsigned int device, unsigned char val);
int smbus_read_byte(unsigned int device, unsigned int address);
int smbus_write_byte(unsigned int device, unsigned int address, unsigned char val);
int smbusx_recv_byte(unsigned int smb_index, unsigned int device);
int smbusx_send_byte(unsigned int smb_index, unsigned int device, unsigned char val);
int smbusx_read_byte(unsigned int smb_index, unsigned int device, unsigned int address);
int smbusx_write_byte(unsigned int smb_index, unsigned int device, unsigned int address,
unsigned char val);
#endif /* !ENV_RAMSTAGE */

6
src/southbridge/nvidia/mcp55/nic.c
View File

@ -29,10 +29,10 @@
#include "chip.h"
#include "mcp55.h"
static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
static int phy_read(u8 *base, unsigned int phy_addr, unsigned int phy_reg)
{
u32 dword;
unsigned loop = 0x100;
unsigned int loop = 0x100;
write32(base + 0x190, 0x8000); /* Clear MDIO lock bit. */
mdelay(1);
@ -61,7 +61,7 @@ static void phy_detect(u8 *base)
{
u32 dword;
int i, val;
unsigned id;
unsigned int id;
dword = read32(base + 0x188);
dword &= ~(1 << 20);

10
src/southbridge/nvidia/mcp55/smbus.c
View File

@ -26,7 +26,7 @@
static int lsmbus_recv_byte(struct device *dev)
{
unsigned device;
unsigned int device;
struct resource *res;
struct bus *pbus;
@ -40,7 +40,7 @@ static int lsmbus_recv_byte(struct device *dev)
static int lsmbus_send_byte(struct device *dev, u8 val)
{
unsigned device;
unsigned int device;
struct resource *res;
struct bus *pbus;
@ -54,7 +54,7 @@ static int lsmbus_send_byte(struct device *dev, u8 val)
static int lsmbus_read_byte(struct device *dev, u8 address)
{
unsigned device;
unsigned int device;
struct resource *res;
struct bus *pbus;
@ -68,7 +68,7 @@ static int lsmbus_read_byte(struct device *dev, u8 address)
static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
{
unsigned device;
unsigned int device;
struct resource *res;
struct bus *pbus;
@ -87,7 +87,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
};
#if CONFIG(HAVE_ACPI_TABLES)
unsigned pm_base;
unsigned int pm_base;
#endif
static void mcp55_sm_read_resources(struct device *dev)

14
src/southbridge/nvidia/mcp55/smbus.h
View File

@ -37,7 +37,7 @@ static inline void smbus_delay(void)
outb(0x80, 0x80);
}
static int smbus_wait_until_done(unsigned smbus_io_base)
static int smbus_wait_until_done(unsigned int smbus_io_base)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
@ -52,7 +52,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
} while (--loops);
return -3;
}
static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device)
{
unsigned char global_status_register;
unsigned char byte;
@ -80,9 +80,9 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
}
return byte;
}
static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)
static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device, unsigned char val)
{
unsigned global_status_register;
unsigned int global_status_register;
outb(val, smbus_io_base + SMBHSTDAT0);
smbus_delay();
@ -110,7 +110,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned
}
return 0;
}
static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address)
{
unsigned char global_status_register;
unsigned char byte;
@ -142,9 +142,9 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
}
static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device, unsigned int address, unsigned char val)
{
unsigned global_status_register;
unsigned int global_status_register;
outb(val, smbus_io_base + SMBHSTDAT0);
smbus_delay();

4
src/southbridge/ricoh/rl5c476/rl5c476.c
View File

@ -193,8 +193,8 @@ static void rl5c476_set_resources(struct device *dev)
}
static void rl5c476_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
static void rl5c476_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
u16 miscreg = pci_read_config16(dev, 0x82);
/* Enable subsystem id register writes */

4
src/southbridge/ti/pci1x2x/pci1x2x.c
View File

@ -38,8 +38,8 @@ static void ti_pci1x2y_init(struct device *dev)
pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02);
}
static void ti_pci1x2y_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
static void ti_pci1x2y_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
/*
* Enable change sub-vendor ID. Clear the bit 5 to enable to write