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src/soc/intel/common: Fix CID 1295499, remove dead code 

Restructure the nvm_is_write_protected routine to eliminate the dead
code error.

TEST=Build and run on Kunimitsu

Change-Id: Ia9170e27d4be3a34760555c48c1635c16f06e6a3
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14337
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Lee Leahy 2016-04-12 13:01:02 -07:00 committed by Leroy P Leahy
parent e03305358f
commit ff7670915c
1 changed files with 21 additions and 20 deletions
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19
src/soc/intel/common/nvm.c
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@ -15,14 +15,13 @@
#include <stdint.h>
#include <stddef.h>
#include <bootmode.h>
#include <console/console.h>
#include <string.h>
#include <spi-generic.h>
#include <spi_flash.h>
#include <soc/spi.h>
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/chromeos.h>
#endif
#include "nvm.h"
/* This module assumes the flash is memory mapped just below 4GiB in the
@ -96,21 +95,21 @@ int nvm_write(void *start, const void *data, size_t size)
/* Read flash status register to determine if write protect is active */
int nvm_is_write_protected(void)
{
u8 sr1;
u8 wp_gpio = 0;
u8 wp_spi;
if (nvm_init() < 0)
return -1;
#if IS_ENABLED(CONFIG_CHROMEOS)
if (IS_ENABLED(CONFIG_CHROMEOS)) {
u8 sr1;
u8 wp_gpio;
u8 wp_spi;
/* Read Write Protect GPIO if available */
wp_gpio = get_write_protect_state();
#endif
/* Read Status Register 1 */
if (flash->status(flash, &sr1) < 0) {
printk(BIOS_ERR, "Failed to read SPI status register 1\n");
printk(BIOS_ERR,
"Failed to read SPI status register 1\n");
return -1;
}
wp_spi = !!(sr1 & 0x80);
@ -120,6 +119,8 @@ int nvm_is_write_protected(void)
return wp_gpio && wp_spi;
}
return 0;
}
/* Apply protection to a range of flash */
int nvm_protect(void *start, size_t size)