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mb/system76/adl: Switch from S0ix to S3 

After fixing TPM logs clobbering other regions in CB:73297, S3 no longer
causes cache issues resulting in power off after multiple suspends.

This is required for disabling Intel CSME by default.

Change-Id: I7eef4c883fd65db93dae81adabd895b2de90496a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
This commit is contained in:
Tim Crawford 2023-07-13 09:44:09 -06:00 committed by Felix Held
parent f501128536
commit ff865a329f
2 changed files with 4 additions and 2 deletions
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4
src/mainboard/system76/adl/Kconfig
View File

@ -7,6 +7,7 @@ config BOARD_SYSTEM76_ADL_COMMON
select DRIVERS_INTEL_PMC select DRIVERS_INTEL_PMC
select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_INTEL_USB4_RETIMER
select EC_SYSTEM76_EC select EC_SYSTEM76_EC
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE select HAVE_OPTION_TABLE
@ -101,6 +102,9 @@ config MAINBOARD_VERSION
config CONSOLE_POST config CONSOLE_POST
default y default y
config D3COLD_SUPPORT
default n
config DIMM_SPD_SIZE config DIMM_SPD_SIZE
default 512 default 512

2
src/mainboard/system76/adl/devicetree.cb
View File

@ -11,8 +11,6 @@ chip soc/intel/alderlake
# Enable Enhanced Intel SpeedStep # Enable Enhanced Intel SpeedStep
register "eist_enable" = "1" register "eist_enable" = "1"
register "s0ix_enable" = "1"
# Enable C6 DRAM # Enable C6 DRAM
register "enable_c6dram" = "1" register "enable_c6dram" = "1"