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asus/f2a85-m: Switch away from AGESA_LEGACY_WRAPPER 

Change-Id: I5a6373ac03d942cd16905c9e8360f7179b8eea61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki 2017-03-04 07:33:35 +02:00
parent 8176af91e8
commit ffa527002a
4 changed files with 41 additions and 73 deletions
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50
src/mainboard/asus/f2a85-m/BiosCallOuts.c
View File

@ -15,13 +15,12 @@
#include "AGESA.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <cbfs.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
#include <stdlib.h>
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
{AGESA_DO_RESET, agesa_Reset },
@ -31,7 +30,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
};
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
@ -86,38 +84,18 @@ static const CODEC_TBL_LIST CodecTableList[] =
{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
};
/**
* Fch Oem setting callback
*
* Configure platform specific Hudson device,
* such Azalia, SATA, GEC, IMC etc.
*/
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
{
AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams_reset->FchReset.Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
} else if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
/* Azalia Controller OEM Codec Table Pointer */
FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
/* Azalia Controller Front Panel OEM Table Pointer */
FchParams_env->Imc.ImcEnable = FALSE;
FchParams_env->Hwm.HwMonitorEnable = FALSE;
FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
/* XHCI configuration */
FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams_env->Usb.Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
}
printk(BIOS_DEBUG, "Done\n");
return AGESA_SUCCESS;
FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
}
void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
{
/* Azalia Controller OEM Codec Table Pointer */
FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
/* Fan Control */
FchParams_env->Imc.ImcEnable = FALSE;
FchParams_env->Hwm.HwMonitorEnable = FALSE;
FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
}

1
src/mainboard/asus/f2a85-m/Kconfig
View File

@ -18,7 +18,6 @@ if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select AGESA_LEGACY_WRAPPER
select CPU_AMD_AGESA_FAMILY15_TN
select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
select SOUTHBRIDGE_AMD_AGESA_HUDSON

58
src/mainboard/asus/f2a85-m/OemCustomize.c
View File

@ -17,7 +17,7 @@
#include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h>
@ -123,6 +123,13 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
&DdiList[0]
};
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
}
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
@ -139,7 +146,7 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
**/
/*---------------------------------------------------------------------------------------*/
static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *TrinityPcieComplexListPtr;
@ -190,14 +197,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
return AGESA_SUCCESS;
}
static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
{
/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@ -205,14 +204,13 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
*----------------------------------------------------------------------------------------
*/
#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M) || IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO)
/*
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
static CONST PSO_ENTRY ROMDATA MemoryTable_M[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
@ -225,29 +223,25 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
*/
PSO_END
};
#elif IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE)
/*
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
static CONST PSO_ENTRY ROMDATA MemoryTable_M_LE[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
/*
TODO: is this OK for DDR3 socket FM2?
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
*/
PSO_END
};
#endif /* CONFIG_BOARD_ASUS_F2A85_M */
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
.InitMid = OemInitMid,
};
void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
{
if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M) || IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO))
InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_M;
else if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE))
InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_M_LE;
}
void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
{
/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
}

5
src/mainboard/asus/f2a85-m/mainboard.c
View File

@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <arch/acpi.h>
@ -45,9 +45,6 @@ static void mainboard_enable(device_t dev)
msr = rdmsr(0xC0011023);
msr.lo &= ~(1 << 23);
wrmsr(0xC0011023, msr);
if (acpi_is_wakeup_s3())
agesawrapper_fchs3earlyrestore();
}
struct chip_operations mainboard_ops = {