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soc/intel/jasperlake: Update C-States info 

- Update C-States max latency values
- Remove MSR programming for C-States latency

BRANCH=None
TEST=Boot to OS and check CState Latenecy
>cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}
POLL
C1_ACPI
C2_ACPI
C3_ACPI
0
1
253
1048

Change-Id: I05c0b5b31d1883f72ca94171aa1b536621e97449
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40902
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ronak Kanabar 2020-04-30 12:07:16 +05:30 committed by Patrick Georgi
parent e585f5b5cc
commit ffb5811b32
3 changed files with 20 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
src/soc/intel/jasperlake/acpi.c
View File

@ -52,70 +52,70 @@ enum {
static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
[C_STATE_C0] = {},
[C_STATE_C1] = {
.latency = 0,
.latency = C1_LATENCY,
.power = C1_POWER,
.resource = MWAIT_RES(0, 0),
},
[C_STATE_C1E] = {
.latency = 0,
.latency = C1_LATENCY,
.power = C1_POWER,
.resource = MWAIT_RES(0, 1),
},
[C_STATE_C6_SHORT_LAT] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
.latency = C6_LATENCY,
.power = C6_POWER,
.resource = MWAIT_RES(2, 0),
},
[C_STATE_C6_LONG_LAT] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
.latency = C6_LATENCY,
.power = C6_POWER,
.resource = MWAIT_RES(2, 1),
},
[C_STATE_C7_SHORT_LAT] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
.latency = C7_LATENCY,
.power = C7_POWER,
.resource = MWAIT_RES(3, 0),
},
[C_STATE_C7_LONG_LAT] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
.latency = C7_LATENCY,
.power = C7_POWER,
.resource = MWAIT_RES(3, 1),
},
[C_STATE_C7S_SHORT_LAT] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
.latency = C7_LATENCY,
.power = C7_POWER,
.resource = MWAIT_RES(3, 2),
},
[C_STATE_C7S_LONG_LAT] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
.latency = C7_LATENCY,
.power = C7_POWER,
.resource = MWAIT_RES(3, 3),
},
[C_STATE_C8] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
.latency = C8_LATENCY,
.power = C8_POWER,
.resource = MWAIT_RES(4, 0),
},
[C_STATE_C9] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
.latency = C9_LATENCY,
.power = C9_POWER,
.resource = MWAIT_RES(5, 0),
},
[C_STATE_C10] = {
.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
.latency = C10_LATENCY,
.power = C10_POWER,
.resource = MWAIT_RES(6, 0),
},
};
static int cstate_set_non_s0ix[] = {
C_STATE_C1E,
C_STATE_C1,
C_STATE_C6_LONG_LAT,
C_STATE_C7S_LONG_LAT
};
static int cstate_set_s0ix[] = {
C_STATE_C1E,
C_STATE_C1,
C_STATE_C7S_LONG_LAT,
C_STATE_C10
};

36
src/soc/intel/jasperlake/cpu.c
View File

@ -137,39 +137,6 @@ static void set_energy_perf_bias(u8 policy)
wrmsr(IA32_ENERGY_PERF_BIAS, msr);
}
static void configure_c_states(void)
{
msr_t msr;
/* C-state Interrupt Response Latency Control 1 - package C6/C7 short */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr);
/* C-state Interrupt Response Latency Control 2 - package C6/C7 long */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);
/* C-state Interrupt Response Latency Control 3 - package C8 */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_32768_NS |
C_STATE_LATENCY_CONTROL_3_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
/* C-state Interrupt Response Latency Control 4 - package C9 */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_32768_NS |
C_STATE_LATENCY_CONTROL_4_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
/* C-state Interrupt Response Latency Control 5 - package C10 */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_32768_NS |
C_STATE_LATENCY_CONTROL_5_LIMIT;
wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
}
/* All CPUs including BSP will run the following function. */
void soc_core_init(struct device *cpu)
{
@ -183,9 +150,6 @@ void soc_core_init(struct device *cpu)
enable_lapic_tpr();
setup_lapic();
/* Configure c-state interrupt response time */
configure_c_states();
/* Configure Enhanced SpeedStep and Thermal Sensors */
configure_misc();

14
src/soc/intel/jasperlake/include/soc/cpu.h
View File

@ -5,13 +5,13 @@
#include <intelblocks/msr.h>
/* Latency times in units of 32768ns */
#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x9d
#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x9d
#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x9d
#define C_STATE_LATENCY_CONTROL_3_LIMIT 0x9d
#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x9d
#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x9d
/* Latency times in us */
#define C1_LATENCY 1
#define C6_LATENCY 127
#define C7_LATENCY 253
#define C8_LATENCY 260
#define C9_LATENCY 487
#define C10_LATENCY 1048
/* Power in units of mW */
#define C1_POWER 0x3e8