- Adds support for the Advantech eval board. Configuration was produced
on a SOM-DB2301 baseboard with a SOM-2354 cpu module. - Also does a slight tweak to the ram test code to make it more obvious when it fails. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Richard Smith
parent
4b539d78ab
commit
ffb7d8a31a
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@ -0,0 +1,143 @@
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#object reset.o
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit ./auto.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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chip northbridge/amd/gx2
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device pci_domain 0 on
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device pci 0.0 on end
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chip southbridge/amd/cs5535
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device pci 12.0 on
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device pci 12.1 off end # SMI
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device pci 12.2 on end # IDE
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device pci 12.3 off end # Audio
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device pci 12.4 off end # VGA
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end
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end
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end
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chip cpu/amd/model_gx2
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end
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end
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@ -0,0 +1,160 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses HAVE_OPTION_TABLE
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uses USE_OPTION_TABLE
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uses CONFIG_ROM_STREAM
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uses IRQ_SLOT_COUNT
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uses MAINBOARD
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PART_NUMBER
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uses LINUXBIOS_EXTRA_VERSION
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uses ARCH
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uses FALLBACK_SIZE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses _RAMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses HAVE_MP_TABLE
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses CONFIG_CONSOLE_SERIAL8250
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uses TTYS0_BAUD
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uses TTYS0_BASE
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uses TTYS0_LCS
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uses CONFIG_UDELAY_TSC
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE = 256*1024
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###
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### Build options
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###
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## no MP table
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##
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default HAVE_MP_TABLE=0
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=0
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## Delay timer options
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##
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default CONFIG_UDELAY_TSC=1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=2
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#object irq_tables.o
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=0
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###
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### LinuxBIOS layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 65536
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default FALLBACK_SIZE = 131072
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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default HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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default USE_OPTION_TABLE = 0
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default _RAMBASE = 0x00004000
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default CONFIG_ROM_STREAM = 1
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##
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## The default compiler
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##
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default CROSS_COMPILE=""
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default CC="$(CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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##
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## The Serial Console
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##
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# To Enable the Serial Console
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default CONFIG_CONSOLE_SERIAL8250=1
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## Select the serial console baud rate
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default TTYS0_BAUD=115200
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#default TTYS0_BAUD=57600
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#default TTYS0_BAUD=38400
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#default TTYS0_BAUD=19200
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#default TTYS0_BAUD=9600
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#default TTYS0_BAUD=4800
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#default TTYS0_BAUD=2400
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#default TTYS0_BAUD=1200
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# Select the serial console base port
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default TTYS0_BASE=0x3f8
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# Select the serial protocol
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# This defaults to 8 data bits, 1 stop bit, and no parity
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default TTYS0_LCS=0x3
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##
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### Select the linuxBIOS loglevel
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##
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## EMERG 1 system is unusable
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## ALERT 2 action must be taken immediately
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## CRIT 3 critical conditions
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## ERR 4 error conditions
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## WARNING 5 warning conditions
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## NOTICE 6 normal but significant condition
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## INFO 7 informational
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## DEBUG 8 debug-level messages
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## SPEW 9 Way too many details
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## Request this level of debugging output
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default DEFAULT_CONSOLE_LOGLEVEL=8
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## At a maximum only compile in this level of debugging
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default MAXIMUM_CONSOLE_LOGLEVEL=8
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end
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@ -0,0 +1,134 @@
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "superio/NSC/pc87360/pc87360_early_serial.c"
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/gx2def.h>
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#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
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#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
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#include "southbridge/amd/cs5535/cs5535_early_setup.c"
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#include "northbridge/amd/gx2/raminit.h"
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/* this has to be done on a per-mainboard basis, esp. if you don't have smbus */
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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{
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msr_t msr;
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/* 1. Initialize GLMC registers base on SPD values,
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* Hard coded as XpressROM for now */
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//print_debug("sdram_enable step 1\r\n");
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msr = rdmsr(0x20000018);
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msr.hi = 0x10075012;
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msr.lo = 0x3900;
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wrmsr(0x20000018, msr);
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msr = rdmsr(0x20000019);
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msr.hi = 0x18000008;
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msr.lo = 0x696332a3;
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wrmsr(0x20000019, msr);
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}
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#include "northbridge/amd/gx2/raminit.c"
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#include "sdram/generic_sdram.c"
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#define PLLMSRhi 0x00000226
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#define PLLMSRlo 0x00000008
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#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
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#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
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#include "northbridge/amd/gx2/pll_reset.c"
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static void msr_init(void)
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{
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__builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
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__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
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__builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
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__builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
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__builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
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__builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
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__builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
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__builtin_wrmsr(0x10000080, 0x3, 0x0);
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__builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
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__builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
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__builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
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__builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef);
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__builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
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__builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
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__builtin_wrmsr(0x50002001, 0x27, 0x0);
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__builtin_wrmsr(0x4c002001, 0x1, 0x0);
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}
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static void main(unsigned long bist)
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{
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static const struct mem_controller memctrl [] = {
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{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
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};
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unsigned char temp;
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msr_init();
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pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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cs5535_early_setup();
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print_err("done cs5535 early\n");
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pll_reset();
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print_err("done pll_reset\n");
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/* Halt if there was a built in self test failure */
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//report_bist_failure(bist);
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sdram_initialize(1, memctrl);
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print_err("Done sdram_initialize\n");
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print_err("Disable watchdog\n");
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outb( 0x87, 0x4E); //enter SuperIO configuration mode
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||||
outb( 0x87, 0x4E);
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||||
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||||
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outb(0x20, 0x4e);
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temp = inb(0x4f);
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||||
print_debug_hex8(temp);
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||||
if (temp != 0x52){
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print_err("CAN NOT READ SUPERIO VID\n");
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||||
}
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||||
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||||
outb(0x29, 0x4e);
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||||
outb(0x7c, 0x4f);
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||||
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||||
outb( 0x07, 0x4E); //enable logical device 9
|
||||
outb( 0x09, 0x4F);
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||||
outb(0x30, 0x4e);
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||||
outb(1, 0x4f);
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||||
outb( 0xF0, 0x4E); //set GP33 as outbut in configuration register F0h Bit4 = \u20180\u2019
|
||||
outb( 0xC7, 0x4F);
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||||
outb( 0xF1, 0x4E); //clr GP33 (Bit4) value in cofiguration register F1h to \u20181\u2019 disables
|
||||
temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!
|
||||
print_debug_hex8(temp);print_debug(":");
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||||
temp = temp & ~8;
|
||||
outb( temp, 0x4F);
|
||||
temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!
|
||||
print_debug_hex8(temp);print_debug("\n");
|
||||
/* Check all of memory */
|
||||
// ram_check(0, 16384);
|
||||
// ram_check(0x20000, 0x24000);
|
||||
// ram_check(0x00000000, 640*1024);
|
||||
|
||||
}
|
||||
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|
@ -0,0 +1,5 @@
|
|||
extern struct chip_operations mainboard_advantech_som_gx533c_ops;
|
||||
|
||||
struct mainboard_advantech_som_gx533c_config {
|
||||
int nothing;
|
||||
};
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
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||||
#8 8 r 0 alarm_seconds
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||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
1008 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 1007 1008
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
|
||||
static void print_debug_pci_dev(unsigned dev)
|
||||
{
|
||||
print_debug("PCI: ");
|
||||
print_debug_hex8((dev >> 16) & 0xff);
|
||||
print_debug_char(':');
|
||||
print_debug_hex8((dev >> 11) & 0x1f);
|
||||
print_debug_char('.');
|
||||
print_debug_hex8((dev >> 8) & 7);
|
||||
}
|
||||
|
||||
static void print_pci_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(0, 0, 0);
|
||||
dev <= PCI_DEV(0, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
uint32_t id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
print_debug_pci_dev(dev);
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void dump_pci_device(unsigned dev)
|
||||
{
|
||||
int i;
|
||||
print_debug_pci_dev(dev);
|
||||
print_debug("\r\n");
|
||||
|
||||
for(i = 0; i <= 255; i++) {
|
||||
unsigned char val;
|
||||
if ((i & 0x0f) == 0) {
|
||||
print_debug_hex8(i);
|
||||
print_debug_char(':');
|
||||
}
|
||||
val = pci_read_config8(dev, i);
|
||||
print_debug_char(' ');
|
||||
print_debug_hex8(val);
|
||||
if ((i & 0x0f) == 0x0f) {
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void dump_pci_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(0, 0, 0);
|
||||
dev <= PCI_DEV(0, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
uint32_t id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
dump_pci_device(dev);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
#define ASSEMBLY 1
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include "arch/romcc_io.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
|
||||
static unsigned long main(unsigned long bist)
|
||||
{
|
||||
/* This is the primary cpu how should I boot? */
|
||||
if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
asm volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
cpu_reset:
|
||||
asm volatile ("jmp __cpu_reset"
|
||||
: /* outputs */
|
||||
: "a"(bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
fallback_image:
|
||||
return bist;
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
* Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
|
||||
*
|
||||
* Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*2, /* there can be total 2 devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
|
||||
0x800, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1078, /* Vendor */
|
||||
0x2, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
|
||||
{0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
|
||||
}
|
||||
};
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
}
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <arch/io.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations mainboard_advantech_som_gx533c_ops = {
|
||||
CHIP_NAME("Advantech SOM GX DB533-C mainboard ")
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
#if 0
|
||||
//#include "arch/romcc_io.h"
|
||||
#include <arch/io.h>
|
||||
|
||||
typedef unsigned device_t;
|
||||
|
||||
#define PCI_DEV(BUS, DEV, FN) ( \
|
||||
(((BUS) & 0xFF) << 16) | \
|
||||
(((DEV) & 0x1f) << 11) | \
|
||||
(((FN) & 0x7) << 8))
|
||||
|
||||
static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
outb(value, 0xCFC + (addr & 3));
|
||||
}
|
||||
|
||||
static void pci_write_config32(device_t dev, unsigned where, unsigned value)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
outl(value, 0xCFC);
|
||||
}
|
||||
|
||||
static unsigned pci_read_config32(device_t dev, unsigned where)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
return inl(0xCFC);
|
||||
}
|
||||
|
||||
#include "../../../northbridge/amd/amdk8/reset_test.c"
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -69,17 +69,26 @@ static void ram_verify(unsigned long start, unsigned long stop)
|
|||
value = read_phys(addr);
|
||||
if (value != addr) {
|
||||
/* Display address with error */
|
||||
print_err("Fail: @0x");
|
||||
print_err_hex32(addr);
|
||||
print_err_char(':');
|
||||
print_err(" Read value=0x");
|
||||
print_err_hex32(value);
|
||||
print_err("\r\n");
|
||||
i++;
|
||||
if(i>256) break;
|
||||
if(i>256) {
|
||||
print_debug("Aborting.\n\r");
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Display final address */
|
||||
print_debug_hex32(addr);
|
||||
print_debug("\r\nDRAM verified\r\n");
|
||||
if (i) {
|
||||
print_debug("\r\nDRAM did _NOT_ verify!\r\n");
|
||||
}
|
||||
else {
|
||||
print_debug("\r\nDRAM range verified.\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,37 @@
|
|||
# Config file for the Advantech eval kit with a SOM-DB2301 baseboard
|
||||
# and a SOM 2354 Cpu module. (gx533)
|
||||
# This will make a target directory of som_gx533c
|
||||
|
||||
target som_gx533c
|
||||
mainboard advantech/som_gx533c
|
||||
|
||||
option ROM_SIZE=1024*512
|
||||
|
||||
option MAXIMUM_CONSOLE_LOGLEVEL=9
|
||||
option DEFAULT_CONSOLE_LOGLEVEL=9
|
||||
|
||||
romimage "normal"
|
||||
option USE_FALLBACK_IMAGE=0
|
||||
option ROM_IMAGE_SIZE=0x10000
|
||||
option LINUXBIOS_EXTRA_VERSION=".0Normal"
|
||||
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
|
||||
# payload ../../../../tg3--ide_disk.zelf
|
||||
# payload ../../../../../lnxieepro100.ebi
|
||||
payload /etc/hosts
|
||||
# payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
|
||||
# payload /tmp/filo.elf
|
||||
end
|
||||
|
||||
romimage "fallback"
|
||||
option USE_FALLBACK_IMAGE=1
|
||||
option ROM_IMAGE_SIZE=0x10000
|
||||
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
|
||||
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
|
||||
# payload ../../../../tg3--ide_disk.zelf
|
||||
# payload ../../../../../lnxieepro100.ebia
|
||||
payload /etc/hosts
|
||||
# payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
|
||||
# payload /tmp/filo.elf
|
||||
end
|
||||
|
||||
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
|
||||
Loading…
Reference in New Issue