mb/google/zork: Fix pad configurations for wake signals
This change updates the pad configurations for wake lines as follows: 1. Pen eject wake signal needs to be configured as PAD_WAKE i.e. wake using GPIO controller block. This is because pen eject signal is not dual routed and the trigger filtering is set by the kernel driver differently for S0 and S3 wake. Hence, it cannot use SCI GEVENT and instead has to fall back to using GPIO controller wake. 2. All other wake signals (EC, trackpad, fingerprint) need to be configured as SCI. This allows OS to enable/disable wake from these sources if required. Example: powerd disables wake from trackpad when in tablet mode. Hence, all other wake sources use SCI. BUG=b:159832123 TEST=Verified wake using pen eject and EC. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Id8cd5926f223db51a689ed8948040b8070cf1680 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42951 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -13,7 +13,7 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = {
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/* PEN_POWER_EN - reset */
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PAD_GPO(GPIO_5, LOW),
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/* EC_FCH_WAKE_L */
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PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
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PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
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/* PCIE_RST1_L - Variable timings (May remove) */
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PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
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/* NVME_AUX_RESET_L */
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@ -46,7 +46,7 @@ static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
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/* EN_PWR_TOUCHPAD_PS2 - reset */
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PAD_GPO(GPIO_6, LOW),
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/* EC_FCH_WAKE_L */
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PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
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PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
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/* PCIE_RST1_L - Variable timings (May remove) */
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PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
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/* NVME_AUX_RESET_L */
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@ -80,7 +80,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
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/* PCIE_WAKE_L */
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PAD_NF(GPIO_2, WAKE_L, PULL_UP),
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/* PEN_DETECT_ODL */
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PAD_GPI(GPIO_4, PULL_UP),
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PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3),
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/* PEN_POWER_EN - Enabled*/
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PAD_GPO(GPIO_5, HIGH),
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/* EN_PWR_TOUCHPAD */
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@ -90,8 +90,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
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/* I2S_LRCLK - Bit banged in depthcharge */
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PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
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/* TOUCHPAD_INT_ODL */
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/* TODO: Make sure driver sets as wake source */
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PAD_GPI(GPIO_9, PULL_UP),
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PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW),
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/* S0iX SLP - (unused - goes to EC & FPMCU */
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PAD_GPI(GPIO_10, PULL_UP),
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/* EC_IN_RW_OD */
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@ -13,7 +13,7 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = {
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/* PEN_POWER_EN - reset */
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PAD_GPO(GPIO_5, LOW),
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/* EC_FCH_WAKE_L */
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PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
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PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
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/* NVME_AUX_RESET_L */
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PAD_GPO(GPIO_40, HIGH),
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/* EN_PWR_TOUCHPAD_PS2 - reset */
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@ -42,7 +42,7 @@ static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
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/* EN_PWR_TOUCHPAD_PS2 - reset */
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PAD_GPO(GPIO_13, LOW),
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/* EC_FCH_WAKE_L */
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PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
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PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
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/* NVME_AUX_RESET_L */
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PAD_GPO(GPIO_40, HIGH),
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/* EMMC_RESET - reset (default stuffing unused)*/
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@ -76,14 +76,13 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
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/* PEN_POWER_EN - Enabled*/
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PAD_GPO(GPIO_5, HIGH),
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/* FPMCU_INT_L */
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PAD_WAKE(GPIO_6, PULL_UP, EDGE_LOW, S3_S4_S5),
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PAD_SCI(GPIO_6, PULL_NONE, EDGE_LOW),
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/* I2S_SDIN */
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PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE),
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/* I2S_LRCLK - Bit banged in depthcharge */
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PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
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/* TOUCHPAD_INT_ODL */
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/* TODO: Make sure driver sets as wake source */
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PAD_GPI(GPIO_9, PULL_UP),
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PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW),
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/* S0iX SLP - (unused - goes to EC & FPMCU */
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PAD_GPI(GPIO_10, PULL_UP),
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/* FPMCU_RST_L */
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