soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP calls

Cezanne doesn't have ACPI support yet, but in this case the function
always returns 0, so it can already be used.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1f5e1f31bf1e52988fcef90daf7b93169e21cbb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50126
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/cezanne/chip.c

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi.h>
 #include <device/device.h>
 #include <fsp/api.h>
 #include <soc/southbridge.h>
@@ -12,7 +13,7 @@ static void enable_dev(struct device *dev)
 
 static void soc_init(void *chip_info)
 {
-	fsp_silicon_init(false); /* no S3 support yet */
+	fsp_silicon_init(acpi_is_wakeup_s3());
 
 	fch_init(chip_info);
 }

src/soc/amd/cezanne/romstage.c

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi.h>
 #include <arch/cpu.h>
 #include <console/console.h>
 #include <fsp/api.h>
@@ -19,7 +20,7 @@ asmlinkage void car_stage_entry(void)
 	u32 val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
 
-	fsp_memory_init(false); /* no S3 resume yet */
+	fsp_memory_init(acpi_is_wakeup_s3());
 
 	run_ramstage();
 }