GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/fsp_baytrail: Adjust root port INT routing 

Adjust the root port INT routing based on Bay Trail spec:
Document Number: 538136, Rev. 3.9

Table 241. Interrupt Generated for INT[A-D] Interrupts
             INTA  INTB  INTC  INTD
Root Port 1 INTA# INTB# INTC# INTD#
Root Port 2 INTD# INTA# INTB# INTC#
Root Port 3 INTC# INTD# INTA# INTB#
Root Port 4 INTB# INTC# INTD# INTA#

Change-Id: I22a8c0bc6ad731dfb79385d6e165f1ec0a07507d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12684
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
This commit is contained in:
Martin Roth 2015-12-07 16:50:47 -07:00
parent 6d2c7226cb
commit ffcd9393a4
1 changed files with 10 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/soc/intel/fsp_baytrail/southcluster.c
View File

@ -208,6 +208,16 @@ static void write_pci_config_irqs(void)
if (targ_dev == NULL || new_int_pin < 1) if (targ_dev == NULL || new_int_pin < 1)
continue; continue;
/*
* Adjust the INT routing for the PCIe root ports
* See 'Interrupt Generated for INT[A-D] Interrupts'
* Table 241 in Document Number: 538136, Rev. 3.9
*/
if (PCI_SLOT(targ_dev->path.pci.devfn) == PCIE_DEV &&
targ_dev != irq_dev)
new_int_pin = ((new_int_pin - 1 +
PCI_FUNC(targ_dev->path.pci.devfn)) % 4) + 1;
/* Get the original INT_PIN for record keeping */ /* Get the original INT_PIN for record keeping */
original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);