sb/intel/ibexpeak: Drop Global NVS support
Was copy-pasted from bd82x6x and no mainboard actually needs it. The few globals moved outside the GNVS will be removed, relocated or replaced with acpigen later. Change-Id: I590a355f1bd1e54365b2e329cfdc62384446a15c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49280 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
Kyösti Mälkki
parent
00f11c0290
commit
ffdf1f9503
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@ -1,5 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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Name(\TCRT, 100)
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Name(\TPSV, 90)
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Name(\FLVL, 0)
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#include <ec/lenovo/h8/acpi/ec.asl>
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#define H8_BAT_THRESHOLDS_BIT7
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@ -1,15 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi_gnvs.h>
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#include <soc/nvs.h>
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void mainboard_fill_gnvs(struct global_nvs *gnvs)
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{
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/* The lid is open by default */
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gnvs->lids = 1;
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/* Temperature at which OS will shutdown */
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gnvs->tcrt = 100;
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/* Temperature at which OS will throttle CPU */
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gnvs->tpsv = 90;
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}
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@ -20,9 +20,6 @@ DefinitionBlock(
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#include "acpi/platform.asl"
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/* global NVS and variables */
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#include <southbridge/intel/ibexpeak/acpi/globalnvs.asl>
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/* General Purpose Events */
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#include "acpi/gpe.asl"
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@ -32,6 +29,9 @@ DefinitionBlock(
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Device (PCI0)
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{
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#include <northbridge/intel/ironlake/acpi/ironlake.asl>
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/* TBD: Remove. */
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Name(\XHCI, 0)
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#include <southbridge/intel/bd82x6x/acpi/pch.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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@ -3,7 +3,6 @@
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#include <arch/io.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <soc/nvs.h>
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#include <southbridge/intel/common/pmutil.h>
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#include <northbridge/intel/ironlake/ironlake.h>
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#include <ec/acpi/ec.h>
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@ -1,5 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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Name(\TCRT, 100)
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Name(\TPSV, 90)
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Name(\FLVL, 0)
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#include <ec/lenovo/h8/acpi/ec.asl>
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Scope(\_SB.PCI0.LPCB.EC)
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@ -1,15 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi_gnvs.h>
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#include <soc/nvs.h>
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void mainboard_fill_gnvs(struct global_nvs *gnvs)
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{
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/* The lid is open by default */
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gnvs->lids = 1;
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/* Temperature at which OS will shutdown */
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gnvs->tcrt = 100;
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/* Temperature at which OS will throttle CPU */
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gnvs->tpsv = 90;
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}
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@ -20,9 +20,6 @@ DefinitionBlock(
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#include "acpi/platform.asl"
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/* global NVS and variables */
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#include <southbridge/intel/ibexpeak/acpi/globalnvs.asl>
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/* General Purpose Events */
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#include "acpi/gpe.asl"
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@ -32,6 +29,9 @@ DefinitionBlock(
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Device (PCI0)
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{
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#include <northbridge/intel/ironlake/acpi/ironlake.asl>
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/* TBD: Remove. */
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Name(\XHCI, 0)
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#include <southbridge/intel/bd82x6x/acpi/pch.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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@ -3,7 +3,6 @@
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#include <arch/io.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <soc/nvs.h>
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#include <southbridge/intel/common/pmutil.h>
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#include <northbridge/intel/ironlake/ironlake.h>
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#include <ec/acpi/ec.h>
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@ -15,9 +15,6 @@ DefinitionBlock(
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#include "acpi/platform.asl"
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/* global NVS and variables */
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#include <southbridge/intel/ibexpeak/acpi/globalnvs.asl>
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/* General Purpose Events */
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#include "acpi/gpe.asl"
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@ -27,6 +24,9 @@ DefinitionBlock(
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Device (PCI0)
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{
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#include <northbridge/intel/ironlake/acpi/ironlake.asl>
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/* TBD: Remove. */
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Name(\XHCI, 0)
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#include <southbridge/intel/bd82x6x/acpi/pch.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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@ -3,7 +3,6 @@
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <device/pci_ops.h>
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#include <soc/nvs.h>
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#include <southbridge/intel/common/pmutil.h>
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#include <northbridge/intel/ironlake/ironlake.h>
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#include <ec/acpi/ec.h>
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@ -5,6 +5,8 @@ Name(_CID,EISAID("PNP0A03")) // PCI
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Name(_BBN, 0)
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Name(\PPCM, 0)
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Device (MCHC)
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{
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Name(_ADR, 0x00000000) // 0:0.0
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@ -8,7 +8,6 @@ if SOUTHBRIDGE_INTEL_IBEXPEAK
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config SOUTH_BRIDGE_OPTIONS
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ACPI_SOC_NVS
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select AZALIA_PLUGIN_SUPPORT
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select IOAPIC
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select HAVE_SMI_HANDLER
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@ -1,219 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Global Variables */
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Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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/* Miscellaneous */
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, 16, // 0x00 - Operating System
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SMIF, 8, // 0x02 - SMI function
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PRM0, 8, // 0x03 - SMI function parameter
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PRM1, 8, // 0x04 - SMI function parameter
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SCIF, 8, // 0x05 - SCI function
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PRM2, 8, // 0x06 - SCI function parameter
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PRM3, 8, // 0x07 - SCI function parameter
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LCKF, 8, // 0x08 - Global Lock function for EC
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PRM4, 8, // 0x09 - Lock function parameter
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PRM5, 8, // 0x0a - Lock function parameter
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P80D, 32, // 0x0b - Debug port (IO 0x80) value
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LIDS, 8, // 0x0f - LID state (open = 1)
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, 8, // 0x10 - Power State (AC = 1)
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/* Thermal policy */
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Offset (0x11),
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TLVL, 8, // 0x11 - Throttle Level Limit
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FLVL, 8, // 0x12 - Current FAN Level
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TCRT, 8, // 0x13 - Critical Threshold
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TPSV, 8, // 0x14 - Passive Threshold
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TMAX, 8, // 0x15 - CPU Tj_max
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F0OF, 8, // 0x16 - FAN 0 OFF Threshold
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F0ON, 8, // 0x17 - FAN 0 ON Threshold
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F0PW, 8, // 0x18 - FAN 0 PWM value
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F1OF, 8, // 0x19 - FAN 1 OFF Threshold
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F1ON, 8, // 0x1a - FAN 1 ON Threshold
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F1PW, 8, // 0x1b - FAN 1 PWM value
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F2OF, 8, // 0x1c - FAN 2 OFF Threshold
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F2ON, 8, // 0x1d - FAN 2 ON Threshold
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F2PW, 8, // 0x1e - FAN 2 PWM value
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F3OF, 8, // 0x1f - FAN 3 OFF Threshold
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F3ON, 8, // 0x20 - FAN 3 ON Threshold
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F3PW, 8, // 0x21 - FAN 3 PWM value
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F4OF, 8, // 0x22 - FAN 4 OFF Threshold
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F4ON, 8, // 0x23 - FAN 4 ON Threshold
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F4PW, 8, // 0x24 - FAN 4 PWM value
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TMPS, 8, // 0x25 - Temperature Sensor ID
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/* Processor Identification */
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Offset (0x28),
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, 8, // 0x28 - Enabled by coreboot
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, 8, // 0x29 - Multi Processor Enable
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PCP0, 8, // 0x2a - PDC CPU/CORE 0
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PCP1, 8, // 0x2b - PDC CPU/CORE 1
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PPCM, 8, // 0x2c - Max. PPC state
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, 8, // 0x2d - Processor count
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/* Super I/O & CMOS config */
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Offset (0x32),
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NATP, 8, // 0x32 -
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S5U0, 8, // 0x33 - Enable USB0 in S5
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S5U1, 8, // 0x34 - Enable USB1 in S5
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S3U0, 8, // 0x35 - Enable USB0 in S3
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S3U1, 8, // 0x36 - Enable USB1 in S3
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S33G, 8, // 0x37 - Enable 3G in S3
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, 32, // 0x38 - CBMEM TOC
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/* Integrated Graphics Device */
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Offset (0x3c),
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IGDS, 8, // 0x3c - IGD state (primary = 1)
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TLST, 8, // 0x3d - Display Toggle List pointer
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CADL, 8, // 0x3e - Currently Attached Devices List
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PADL, 8, // 0x3f - Previously Attached Devices List
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/* Backlight Control */
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Offset (0x64),
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BLCS, 8, // 0x64 - Backlight control possible?
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BRTL, 8, // 0x65 - Brightness Level
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ODDS, 8, // 0x66
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/* Ambient Light Sensors */
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Offset (0x6e),
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ALSE, 8, // 0x6e - ALS enable
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ALAF, 8, // 0x6f - Ambient light adjustment factor
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LLOW, 8, // 0x70 - LUX Low
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LHIH, 8, // 0x71 - LUX High
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/* EMA */
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Offset (0x78),
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EMAE, 8, // 0x78 - EMA enable
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EMAP, 16, // 0x79 - EMA pointer
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EMAL, 16, // 0x7b - EMA length
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/* MEF */
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Offset (0x82),
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MEFE, 8, // 0x82 - MEF enable
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/* TPM support */
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Offset (0x8c),
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TPMP, 8, // 0x8c - TPM
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TPME, 8, // 0x8d - TPM enable
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/* SATA */
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Offset (0x96),
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GTF0, 56, // 0x96 - GTF task file buffer for port 0
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GTF1, 56, // 0x9d - GTF task file buffer for port 1
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GTF2, 56, // 0xa4 - GTF task file buffer for port 2
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IDEM, 8, // 0xab - IDE mode (compatible / enhanced)
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IDET, 8, // 0xac - IDE
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/* XHCI */
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Offset (0xb2),
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XHCI, 8,
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CBMC, 32,
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PM1I, 32, // System Wake Source - PM1 Index
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GPEI, 32, // GPE Wake Source
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}
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/* Set flag to enable USB charging in S3 */
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Method (S3UE)
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{
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Store (One, \S3U0)
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Store (One, \S3U1)
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}
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/* Set flag to disable USB charging in S3 */
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Method (S3UD)
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{
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Store (Zero, \S3U0)
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Store (Zero, \S3U1)
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}
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/* Set flag to enable USB charging in S5 */
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Method (S5UE)
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{
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Store (One, \S5U0)
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Store (One, \S5U1)
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}
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/* Set flag to disable USB charging in S5 */
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Method (S5UD)
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{
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Store (Zero, \S5U0)
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Store (Zero, \S5U1)
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}
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/* Set flag to enable 3G module in S3 */
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Method (S3GE)
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{
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Store (One, \S33G)
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}
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/* Set flag to disable 3G module in S3 */
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Method (S3GD)
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{
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Store (Zero, \S33G)
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}
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/* Set XHCI Mode enable */
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Method (XHCE)
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{
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Store (One, \XHCI)
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}
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/* Set XHCI Mode disable */
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Method (XHCD)
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{
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Store (Zero, \XHCI)
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}
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External (\_TZ.SKIN)
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Method (TZUP)
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{
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#ifdef HAVE_THERMALZONE
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/* Update Primary Thermal Zone */
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If (CondRefOf (\_TZ.THRM)) {
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Notify (\_TZ.THRM, 0x81)
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}
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#endif
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/* Update Secondary Thermal Zone */
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If (CondRefOf (\_TZ.SKIN)) {
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Notify (\_TZ.SKIN, 0x81)
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}
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}
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/* Update Fan 0 thresholds */
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Method (F0UT, 2)
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{
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Store (Arg0, \F0OF)
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Store (Arg1, \F0ON)
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TZUP ()
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}
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/* Update Fan 1 thresholds */
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Method (F1UT, 2)
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{
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Store (Arg0, \F1OF)
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Store (Arg1, \F1ON)
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TZUP ()
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}
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/* Update Fan 2 thresholds */
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Method (F2UT, 2)
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{
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Store (Arg0, \F2OF)
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Store (Arg1, \F2ON)
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TZUP ()
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}
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/* Update Fan 3 thresholds */
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Method (F3UT, 2)
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{
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Store (Arg0, \F3OF)
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Store (Arg1, \F3ON)
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TZUP ()
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}
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/* Update Fan 4 thresholds */
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Method (F4UT, 2)
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{
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Store (Arg0, \F4OF)
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Store (Arg1, \F4ON)
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TZUP ()
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}
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/* Update Temperature Sensor ID */
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Method (TMPU, 1)
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{
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Store (Arg0, \TMPS)
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TZUP ()
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}
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@ -1,109 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H
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#define SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H
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#include <commonlib/helpers.h>
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#include <stdint.h>
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struct __packed global_nvs {
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/* Miscellaneous */
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u16 unused_was_osys; /* 0x00 - Operating System */
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u8 smif; /* 0x02 - SMI function call ("TRAP") */
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u8 prm0; /* 0x03 - SMI function call parameter */
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u8 prm1; /* 0x04 - SMI function call parameter */
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u8 scif; /* 0x05 - SCI function call (via _L00) */
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u8 prm2; /* 0x06 - SCI function call parameter */
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u8 prm3; /* 0x07 - SCI function call parameter */
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u8 lckf; /* 0x08 - Global Lock function for EC */
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u8 prm4; /* 0x09 - Lock function parameter */
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u8 prm5; /* 0x0a - Lock function parameter */
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u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
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u8 lids; /* 0x0f - LID state (open = 1) */
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u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
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/* Thermal policy */
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u8 tlvl; /* 0x11 - Throttle Level Limit */
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u8 flvl; /* 0x12 - Current FAN Level */
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u8 tcrt; /* 0x13 - Critical Threshold */
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u8 tpsv; /* 0x14 - Passive Threshold */
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u8 tmax; /* 0x15 - CPU Tj_max */
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u8 f0of; /* 0x16 - FAN 0 OFF Threshold */
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u8 f0on; /* 0x17 - FAN 0 ON Threshold */
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u8 f0pw; /* 0x18 - FAN 0 PWM value */
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u8 f1of; /* 0x19 - FAN 1 OFF Threshold */
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u8 f1on; /* 0x1a - FAN 1 ON Threshold */
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u8 f1pw; /* 0x1b - FAN 1 PWM value */
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u8 f2of; /* 0x1c - FAN 2 OFF Threshold */
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u8 f2on; /* 0x1d - FAN 2 ON Threshold */
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u8 f2pw; /* 0x1e - FAN 2 PWM value */
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u8 f3of; /* 0x1f - FAN 3 OFF Threshold */
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u8 f3on; /* 0x20 - FAN 3 ON Threshold */
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u8 f3pw; /* 0x21 - FAN 3 PWM value */
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u8 f4of; /* 0x22 - FAN 4 OFF Threshold */
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u8 f4on; /* 0x23 - FAN 4 ON Threshold */
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u8 f4pw; /* 0x24 - FAN 4 PWM value */
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u8 tmps; /* 0x25 - Temperature Sensor ID */
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u8 rsvd3[2];
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/* Processor Identification */
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u8 unused_was_apic; /* 0x28 - APIC enabled */
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u8 unused_was_mpen; /* 0x29 - MP capable/enabled */
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u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
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u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
|
||||
u8 ppcm; /* 0x2c - Max. PPC state */
|
||||
u8 unused_was_pcnt; /* 0x2d - Processor Count */
|
||||
u8 rsvd4[4];
|
||||
/* Super I/O & CMOS config */
|
||||
u8 natp; /* 0x32 - SIO type */
|
||||
u8 s5u0; /* 0x33 - Enable USB0 in S5 */
|
||||
u8 s5u1; /* 0x34 - Enable USB1 in S5 */
|
||||
u8 s3u0; /* 0x35 - Enable USB0 in S3 */
|
||||
u8 s3u1; /* 0x36 - Enable USB1 in S3 */
|
||||
u8 s33g; /* 0x37 - Enable S3 in 3G */
|
||||
u32 obsolete_cmem; /* 0x38 - CBMEM TOC */
|
||||
/* Integrated Graphics Device */
|
||||
u8 igds; /* 0x3c - IGD state */
|
||||
u8 tlst; /* 0x3d - Display Toggle List Pointer */
|
||||
u8 cadl; /* 0x3e - currently attached devices */
|
||||
u8 padl; /* 0x3f - previously attached devices */
|
||||
u8 rsvd5[36];
|
||||
/* Backlight Control */
|
||||
u8 blcs; /* 0x64 - Backlight Control possible */
|
||||
u8 brtl;
|
||||
u8 odds;
|
||||
u8 rsvd6[0x7];
|
||||
/* Ambient Light Sensors*/
|
||||
u8 alse; /* 0x6e - ALS enable */
|
||||
u8 alaf;
|
||||
u8 llow;
|
||||
u8 lhih;
|
||||
u8 rsvd7[0x6];
|
||||
/* Extended Mobile Access */
|
||||
u8 emae; /* 0x78 - EMA enable */
|
||||
u16 emap; /* 0x79 - EMA pointer */
|
||||
u16 emal; /* 0x7a - EMA Length */
|
||||
u8 rsvd8[0x5];
|
||||
/* MEF */
|
||||
u8 mefe; /* 0x82 - MEF enable */
|
||||
u8 rsvd9[0x9];
|
||||
/* TPM support */
|
||||
u8 tpmp; /* 0x8c - TPM */
|
||||
u8 tpme;
|
||||
u8 rsvd10[8];
|
||||
/* SATA */
|
||||
u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */
|
||||
u8 gtf1[7];
|
||||
u8 gtf2[7];
|
||||
u8 idem;
|
||||
u8 idet;
|
||||
u8 rsvd11[6];
|
||||
/* XHCI */
|
||||
u8 xhci;
|
||||
|
||||
u32 cbmc;
|
||||
|
||||
/* Required for future unified acpi_save_wake_source. */
|
||||
u32 pm1i;
|
||||
u32 gpei;
|
||||
};
|
||||
|
||||
#endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */
|
||||
|
|
@ -8,7 +8,6 @@
|
|||
#include <cpu/x86/smm.h>
|
||||
#include <cpu/intel/em64t101_save_state.h>
|
||||
#include <cpu/intel/model_2065x/model_2065x.h>
|
||||
#include <soc/nvs.h>
|
||||
#include <southbridge/intel/common/finalize.h>
|
||||
#include <southbridge/intel/common/pmbase.h>
|
||||
#include <southbridge/intel/ibexpeak/me.h>
|
||||
|
|
@ -22,23 +21,6 @@
|
|||
#include <southbridge/intel/common/gpio.h>
|
||||
#include <southbridge/intel/common/pmutil.h>
|
||||
|
||||
int southbridge_io_trap_handler(int smif)
|
||||
{
|
||||
switch (smif) {
|
||||
case 0x32:
|
||||
printk(BIOS_DEBUG, "OS Init\n");
|
||||
/* gnvs->smif:
|
||||
* On success, the IO Trap Handler returns 0
|
||||
* On failure, the IO Trap Handler returns a value != 0
|
||||
*/
|
||||
gnvs->smif = 0;
|
||||
return 1; /* IO trap handled */
|
||||
}
|
||||
|
||||
/* Not handled */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void southbridge_gate_memory_reset_real(int offset,
|
||||
u16 use, u16 io, u16 lvl)
|
||||
{
|
||||
|
|
@ -108,8 +90,6 @@ void southbridge_smi_monitor(void)
|
|||
|
||||
/* IOTRAP(3) SMI function call */
|
||||
if (IOTRAP(3)) {
|
||||
if (gnvs && gnvs->smif)
|
||||
io_trap_handler(gnvs->smif); // call function smif
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue