diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index e2c43f042e..6c64cd9925 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_MICROCODE_IN_CBFS + select GENERIC_GPIO_LIB select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_HARD_RESET select HAVE_MONOTONIC_TIMER diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 79672315cd..28ed07ebd3 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -24,6 +24,201 @@ #include #include + +/* There are 4 communities with 8 GPIO groups (GPP_[A:G] and GPD) */ +struct gpio_community { + int port_id; + /* Inclusive pads within the community. */ + gpio_t min; + gpio_t max; +}; + +/* This is ordered to match ACPI and OS driver. */ +static const struct gpio_community communities[] = { + { + .port_id = PID_GPIOCOM0, + .min = GPP_A0, + .max = GPP_B23, + }, + { + .port_id = PID_GPIOCOM1, + .min = GPP_C0, + .max = GPP_E23, + }, + { + .port_id = PID_GPIOCOM3, + .min = GPP_F0, + .max = GPP_G7, + }, + { + .port_id = PID_GPIOCOM2, + .min = GPD0, + .max = GPD11, + }, +}; + +static const struct gpio_community *gpio_get_community(gpio_t pad) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(communities); i++) { + const struct gpio_community *c = &communities[i]; + + if (pad >= c->min && pad <= c->max) + return c; + } + + return NULL; +} + +static void *gpio_dw_regs(gpio_t pad) +{ + const struct gpio_community *comm; + uint8_t *regs; + size_t pad_relative; + + comm = gpio_get_community(pad); + + if (comm == NULL) + return NULL; + + regs = pcr_port_regs(comm->port_id); + + pad_relative = pad - comm->min; + + /* DW0 and DW1 regs are 4 bytes each. */ + return ®s[PAD_CFG_DW_OFFSET + pad_relative * 8]; +} + +static void *gpio_hostsw_reg(gpio_t pad, size_t *bit) +{ + const struct gpio_community *comm; + uint8_t *regs; + size_t pad_relative; + + comm = gpio_get_community(pad); + + if (comm == NULL) + return NULL; + + regs = pcr_port_regs(comm->port_id); + + pad_relative = pad - comm->min; + + /* Update the bit for this pad. */ + *bit = (pad_relative % HOSTSW_OWN_PADS_PER); + + /* HostSw regs are 4 bytes each. */ + regs = ®s[HOSTSW_OWN_REG_OFFSET]; + return ®s[(pad_relative / HOSTSW_OWN_PADS_PER) * 4]; +} + +static void gpio_handle_pad_mode(const struct pad_config *cfg) +{ + size_t bit; + uint32_t *hostsw_own_reg; + uint32_t reg; + + bit = 0; + hostsw_own_reg = gpio_hostsw_reg(cfg->pad, &bit); + + reg = read32(hostsw_own_reg); + reg &= ~(1U << bit); + + if ((cfg->attrs & PAD_FIELD(HOSTSW, GPIO)) == PAD_FIELD(HOSTSW, GPIO)) + reg |= (HOSTSW_GPIO << bit); + else + reg |= (HOSTSW_ACPI << bit); + + write32(hostsw_own_reg, reg); +} + +static void gpio_configure_pad(const struct pad_config *cfg) +{ + uint32_t *dw_regs; + uint32_t reg; + uint32_t termination; + const uint32_t termination_mask = PAD_TERM_MASK << PAD_TERM_SHIFT; + + dw_regs = gpio_dw_regs(cfg->pad); + + if (dw_regs == NULL) + return; + + write32(&dw_regs[0], cfg->dw0); + reg = read32(&dw_regs[1]); + reg &= ~termination_mask; + termination = cfg->attrs; + termination &= termination_mask; + reg |= termination; + write32(&dw_regs[1], reg); + + gpio_handle_pad_mode(cfg); +} + +void gpio_configure_pads(const struct pad_config *cfgs, size_t num) +{ + size_t i; + + for (i = 0; i < num; i++) + gpio_configure_pad(&cfgs[i]); +} + +void gpio_input_pulldown(gpio_t gpio) +{ + struct pad_config cfg = PAD_CFG_GPI(gpio, 5K_PD, DEEP); + gpio_configure_pad(&cfg); +} + +void gpio_input_pullup(gpio_t gpio) +{ + struct pad_config cfg = PAD_CFG_GPI(gpio, 5K_PU, DEEP); + gpio_configure_pad(&cfg); +} + +void gpio_input(gpio_t gpio) +{ + struct pad_config cfg = PAD_CFG_GPI(gpio, NONE, DEEP); + gpio_configure_pad(&cfg); +} + +void gpio_output(gpio_t gpio, int value) +{ + struct pad_config cfg = PAD_CFG_GPO(gpio, value, DEEP); + gpio_configure_pad(&cfg); +} + +int gpio_get(gpio_t gpio_num) +{ + uint32_t *dw_regs; + uint32_t reg; + + dw_regs = gpio_dw_regs(gpio_num); + + if (dw_regs == NULL) + return -1; + + reg = read32(&dw_regs[0]); + + return (reg >> GPIORXSTATE_SHIFT) & GPIORXSTATE_MASK; +} + +void gpio_set(gpio_t gpio_num, int value) +{ + uint32_t *dw_regs; + uint32_t reg; + + dw_regs = gpio_dw_regs(gpio_num); + + if (dw_regs == NULL) + return; + + reg = read32(&dw_regs[0]); + reg |= PAD_FIELD_VAL(GPIOTXSTATE, value); + write32(&dw_regs[0], reg); + /* GPIO port ids support posted write semantics. */ +} + /* Keep the ordering intact GPP_A ~ G, GPD. * As the gpio/smi functions gpio_get_smi_status() and * gpio_enable_groupsmi() depends on this ordering. @@ -85,7 +280,7 @@ static const GPIO_GROUP_INFO gpio_group_info[] = { .smistsoffset = NO_REGISTER_PROPERTY, .smienoffset = NO_REGISTER_PROPERTY, }, - /* GPP_H */ + /* GPD */ { .community = PID_GPIOCOM2, .padcfgoffset = R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET, @@ -95,156 +290,6 @@ static const GPIO_GROUP_INFO gpio_group_info[] = { }, }; -/* - * SPT has 7 GPIO communities named as GPP_A to GPP_G. - * Each community has 24 GPIO PIN. - * Below formula to calculate GPIO Pin from GPIO PAD. - * PIN# = GROUP_PAD# + GROUP# * 24 - * ==================================== - * Community || Group# - * ==================================== - * GPP_A || 0 - * GPP_B || 1 - * GPP_C || 2 - * GPP_D || 3 - * GPP_E || 4 - * GPP_F || 5 - * GPP_G || 6 - */ -static u32 get_padnumber_from_gpiopad(GPIO_PAD gpiopad) -{ - return (u32) GPIO_GET_PAD_NUMBER(gpiopad); -} - -static u32 get_groupindex_from_gpiopad(GPIO_PAD gpiopad) -{ - return (u32) GPIO_GET_GROUP_INDEX_FROM_PAD(gpiopad); -} - -static int read_write_gpio_pad_reg(u32 gpiopad, u8 dwreg, u32 mask, int write, - u32 *readwriteval) -{ - u32 padcfgreg; - u32 gpiogroupinfolength; - u32 groupindex; - u32 padnumber; - - groupindex = get_groupindex_from_gpiopad(gpiopad); - padnumber = get_padnumber_from_gpiopad(gpiopad); - - gpiogroupinfolength = sizeof(gpio_group_info) / sizeof(GPIO_GROUP_INFO); - - /* Check if group argument exceeds GPIO GROUP INFO array */ - if ((u32) groupindex >= gpiogroupinfolength) - return -1; - /* Check if legal pin number */ - if (padnumber >= gpio_group_info[groupindex].padpergroup) - return -1; - /* Create Pad Configuration register offset */ - padcfgreg = 0x8 * padnumber + gpio_group_info[groupindex].padcfgoffset; - if (dwreg == 1) - padcfgreg += 0x4; - if (write) { - pcr_andthenor32(gpio_group_info[groupindex].community, - padcfgreg, (u32) (~mask), - (u32) (*readwriteval & mask)); - } else { - pcr_read32(gpio_group_info[groupindex].community, padcfgreg, - readwriteval); - *readwriteval &= mask; - } - - return 0; -} - -static int convert_gpio_num_to_pad(gpio_t gpionum) -{ - int group_pad_num = 0; - int gpio_group = 0; - u32 gpio_pad = 0; - - group_pad_num = (gpionum % MAX_GPIO_PIN_PER_GROUP); - gpio_group = (gpionum / MAX_GPIO_PIN_PER_GROUP); - - switch (gpio_group) { - case GPIO_LP_GROUP_A: - gpio_pad = GPIO_LP_GROUP_GPP_A; - break; - - case GPIO_LP_GROUP_B: - gpio_pad = GPIO_LP_GROUP_GPP_B; - break; - - case GPIO_LP_GROUP_C: - gpio_pad = GPIO_LP_GROUP_GPP_C; - break; - - case GPIO_LP_GROUP_D: - gpio_pad = GPIO_LP_GROUP_GPP_D; - break; - - case GPIO_LP_GROUP_E: - gpio_pad = GPIO_LP_GROUP_GPP_E; - break; - - case GPIO_LP_GROUP_F: - gpio_pad = GPIO_LP_GROUP_GPP_F; - break; - - case GPIO_LP_GROUP_G: - gpio_pad = GPIO_LP_GROUP_GPP_G; - break; - default: - return -1; - break; - } - gpio_pad = (gpio_pad << GPIO_GROUP_SHIFT) + group_pad_num; - - return gpio_pad; -} - -int gpio_get(gpio_t gpio_num) -{ - u32 gpiopad = 0; - u32 outputvalue = 0; - int status = 0; - - if (gpio_num > MAX_GPIO_NUMBER) - return 0; - - gpiopad = convert_gpio_num_to_pad(gpio_num); - if (gpiopad < 0) - return -1; - - status = read_write_gpio_pad_reg(gpiopad, - 0, - B_PCH_GPIO_TX_STATE, - READ, &outputvalue); - outputvalue >>= N_PCH_GPIO_TX_STATE; - return outputvalue; -} - -void gpio_set(gpio_t gpio_num, int value) -{ - int status = 0; - u32 gpiopad = 0; - u32 outputvalue = 0; - - if (gpio_num > MAX_GPIO_NUMBER) - return; - - gpiopad = convert_gpio_num_to_pad(gpio_num); - if (gpiopad < 0) - return; - - outputvalue = value; - - status = read_write_gpio_pad_reg(gpiopad, - 0, - B_PCH_GPIO_TX_STATE, - WRITE, &outputvalue); -} - void gpio_clear_all_smi(void) { u32 gpiogroupinfolength; diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index e8438ff99d..a7d9158ed5 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -22,11 +22,14 @@ #define _SOC_GPIO_H_ #include +#include +#include +#include /* SOC has 8 GPIO communities GPP A~G, GPD */ #define GPIO_COMMUNITY_MAX 8 -typedef int gpio_t; +typedef uint32_t gpio_t; /* Clear GPIO SMI Status */ void gpio_clear_all_smi(void); @@ -40,490 +43,106 @@ void gpio_enable_all_smi(void); /* Enable GPIO individual Group SMI */ void gpio_enable_groupsmi(gpio_t gpio_num, u32 mask); -/* - * GPP_Ax to GPP_Gx; - * where x=24 [between GPIO Community A to F] - * = 7 [only for GPIO Community G] - */ -#define MAX_GPIO_NUMBER 151 /* zero based */ -#define GPIO_LIST_END 0xffffffff +/* Configure the pads according to the pad_config array. */ +struct pad_config; +void gpio_configure_pads(const struct pad_config *cfgs, size_t num); + +#define PAD_FIELD_VAL(field_, val_) \ + (((val_) & field_ ## _MASK) << field_ ## _SHIFT) + +#define PAD_FIELD(field_, setting_) \ + PAD_FIELD_VAL(field_, field_ ## _ ## setting_) /* - * Skylake LP GPIO PIN to Pad Mapping + * This encodes all the fields found within the dw0 register for each + * pad. It directly follows the register specification: + * rst - reset type when pad configuration is reset + * rxst - native function routing: raw buffer or internal buffer + * rxraw1 - drive fixed '1' for Rx buffer + * rxev - event filtering for pad value: level, edge, drive '0' + * rxgf - glitch filter enable + * rxinv - invert the internal pad state + * gpiioapic - route to IOxAPIC + * gpisci - route for SCI + * gpismi - route for SMI + * gpinmi - route for NMI + * mode - GPIO vs native function + * rxdis - disable Rx buffer + * txdis - disable Tx buffer */ -#define GPIO_LP_GROUP_A 0x0 -#define GPIO_LP_GROUP_B 0x1 -#define GPIO_LP_GROUP_C 0x2 -#define GPIO_LP_GROUP_D 0x3 -#define GPIO_LP_GROUP_E 0x4 -#define GPIO_LP_GROUP_F 0x5 -#define GPIO_LP_GROUP_G 0x6 +#define _DW0_VALS(rst, rxst, rxraw1, rxev, rxgf, rxinv, gpiioapic, gpisci, \ + gpismi, gpinmi, mode, rxdis, txdis) \ + (PAD_FIELD(PADRSTCFG, rst) | \ + PAD_FIELD(RXPADSTSEL, rxst) | \ + PAD_FIELD(RXRAW1, rxraw1) | \ + PAD_FIELD(RXEVCFG, rxev) | \ + PAD_FIELD(PREGFRXSEL, rxgf) | \ + PAD_FIELD(RXINV, rxinv) | \ + PAD_FIELD(GPIROUTIOXAPIC, gpiioapic) | \ + PAD_FIELD(GPIROUTSCI, gpisci) | \ + PAD_FIELD(GPIROUTSMI, gpismi) | \ + PAD_FIELD(GPIROUTNMI, gpinmi) | \ + PAD_FIELD(PMODE, mode) | \ + PAD_FIELD(GPIORXDIS, rxdis) | \ + PAD_FIELD(GPIOTXDIS, txdis)) -#define GPIO_LP_GROUP_GPP_A 0x0200 -#define GPIO_LP_GROUP_GPP_B 0x0201 -#define GPIO_LP_GROUP_GPP_C 0x0202 -#define GPIO_LP_GROUP_GPP_D 0x0203 -#define GPIO_LP_GROUP_GPP_E 0x0204 -#define GPIO_LP_GROUP_GPP_F 0x0205 -#define GPIO_LP_GROUP_GPP_G 0x0206 +#define _PAD_CFG_ATTRS(pad_, term_, dw0_, attrs_) \ + { \ + .pad = pad_, \ + .attrs = PAD_FIELD(PAD_TERM, term_) | attrs_, \ + .dw0 = dw0_, \ + } -#define GPIO_GROUP_SHIFT 16 -#define MAX_GPIO_PIN_PER_GROUP 24 +#define _PAD_CFG(pad_, term_, dw0_) _PAD_CFG_ATTRS(pad_, term_, dw0_, 0) -/* GPIO TX STATE */ -#define B_PCH_GPIO_TX_STATE 0x0001 -#define N_PCH_GPIO_TX_STATE 0 +/* Native Function - No Rx buffer manipulation */ +#define PAD_CFG_NF(pad_, term_, rst_, func_) \ + _PAD_CFG(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, func_, NO, NO)) -/* Interrupt number */ -#define B_PCH_GPIO_INTSEL 0x7F -#define N_PCH_GPIO_INTSEL 0 +/* General purpose output. By default no termination. */ +#define PAD_CFG_GPO(pad_, val_, rst_) \ + _PAD_CFG(pad_, NONE, \ + _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, YES, NO) \ + | PAD_FIELD_VAL(GPIOTXSTATE, val_)) -/* Structure for storing information about registers offset, community, - * maximal pad number, smi status and smi enable for available groups - */ -typedef struct { - u32 community; - u32 padcfgoffset; - u32 padpergroup; - u32 smistsoffset; - u32 smienoffset; -} GPIO_GROUP_INFO; +/* General purpose input with no special IRQ routing. */ +#define PAD_CFG_GPI(pad_, term_, rst_) \ + _PAD_CFG(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, NO, YES)) + +/* General purpose input passed through to IOxAPIC. Assume APIC logic can + * handle polarity/edge/level constraints. */ +#define PAD_CFG_GPI_APIC(pad_, term_, rst_) \ + _PAD_CFG(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, YES, NO, NO, NO, GPIO, NO, YES)) + +/* General purpose input routed to SCI. This assumes edge triggered events. */ +#define PAD_CFG_GPI_ACPI_SCI(pad_, term_, rst_, inv_) \ + _PAD_CFG_ATTRS(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, EDGE, NO, inv_, \ + NO, YES, NO, NO, GPIO, NO, YES), PAD_FIELD(HOSTSW, ACPI)) + +/* General purpose input routed to SMI. This assumes edge triggered events. */ +#define PAD_CFG_GPI_ACPI_SMI(pad_, term_, rst_, inv_) \ + _PAD_CFG(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, EDGE, NO, inv_, \ + NO, NO, YES, NO, GPIO, NO, YES), PAD_FIELD(HOSTSW, ACPI)) /* - * GPIO Community 0 Registers are for GPP_A and GPP_B groups + * The 'attrs' field carries the termination in bits 13:10 to match up with + * thd DW1 pad configuration register. Additionally, other attributes can + * be applied such as the ones below. Bit allocation matters. */ -#define R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET 0x400 -#define R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET 0x4C0 -#define R_PCH_PCR_GPIO_GPP_A_SMI_STS 0x0180 -#define R_PCH_PCR_GPIO_GPP_B_SMI_STS 0x0184 -#define R_PCH_PCR_GPIO_GPP_A_SMI_EN 0x01A0 -#define R_PCH_PCR_GPIO_GPP_B_SMI_EN 0x01A4 +#define HOSTSW_SHIFT 0 +#define HOSTSW_MASK 1 +#define HOSTSW_ACPI HOSTSW_OWN_ACPI +#define HOSTSW_GPIO HOSTSW_OWN_GPIO -/* - * GPIO Community 1 Registers are for GPP_C, GPP_D, GPP_E groups - */ -#define R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET 0x400 -#define R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET 0x4C0 -#define R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET 0x580 -#define R_PCH_PCR_GPIO_GPP_C_SMI_STS 0x0180 -#define R_PCH_PCR_GPIO_GPP_D_SMI_STS 0x0184 -#define R_PCH_PCR_GPIO_GPP_E_SMI_STS 0x0188 -#define R_PCH_PCR_GPIO_GPP_C_SMI_EN 0x01A0 -#define R_PCH_PCR_GPIO_GPP_D_SMI_EN 0x01A4 -#define R_PCH_PCR_GPIO_GPP_E_SMI_EN 0x01A8 +struct pad_config { + uint16_t pad; + uint16_t attrs; + uint32_t dw0; +}; -/* - * GPIO Community 3 Registers are for GPP_F and GPP_G groups - */ -#define R_PCH_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x400 -#define R_PCH_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x4C0 - -/* - * GPIO Community 2 Registers are for GPP_DSW - */ -#define R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET 0x400 - -#define READ 0 -#define WRITE 1 - -/* If in GPIO_GROUP_INFO structure certain register doesn't exist - * it will have value equal to NO_REGISTER_PROPERTY - */ -#define NO_REGISTER_PROPERTY (~0u) - -#define V_PCH_GPIO_GPP_A_PAD_MAX 24 -#define V_PCH_GPIO_GPP_B_PAD_MAX 24 -#define V_PCH_GPIO_GPP_C_PAD_MAX 24 -#define V_PCH_GPIO_GPP_D_PAD_MAX 24 -#define V_PCH_GPIO_GPP_E_PAD_MAX 24 -#define V_PCH_GPIO_GPP_F_PAD_MAX 24 -#define V_PCH_GPIO_GPP_G_PAD_MAX 8 -#define V_PCH_GPIO_GPD_PAD_MAX 12 - -#define GPIO_GET_GROUP_INDEX(group) (group & 0xFF) -#define GPIO_GET_GROUP_INDEX_FROM_PAD(pad) (\ - GPIO_GET_GROUP_INDEX((pad >> 16))) -#define GPIO_GET_PAD_NUMBER(pad) (pad & 0xFFFF) - -/* Number of pins used by SerialIo controllers */ -#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4 -#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2 - -/* Below defines are based on GPIO_CONFIG structure fields */ -#define GPIO_CONF_PAD_MODE_MASK 0xF -#define GPIO_CONF_PAD_MODE_BIT_POS 0 - -/* GPIO Pad Mode */ -#define B_PCH_GPIO_PAD_MODE (0x1000 | 0x800 | 0x400) -#define N_PCH_GPIO_PAD_MODE 10 - -/* For any GpioPad usage in code use GPIO_PAD type*/ -typedef u32 GPIO_PAD; - -/* For any GpioGroup usage in code use GPIO_GROUP type */ -typedef u32 GPIO_GROUP; - -/* - * GPIO configuration structure used for pin programming. - * Structure contains fields that can be used to configure pad. - */ -typedef struct { - /* - Pad Mode - Pad can be set as GPIO or one of its native functions. - When in native mode setting Direction, OutputState, Interrupt is unnecessary. - Refer to definition of GPIO_PAD_MODE. - Refer to EDS for each native mode according to the pad. - */ - u32 PadMode : 4; - /* - Host Software Pad Ownership - Set pad to ACPI mode or GPIO Driver Mode. - Refer to definition of GPIO_HOSTSW_OWN. - */ - u32 HostSoftPadOwn : 2; - /* - GPIO Direction - Can choose between In, In with inversion Out, both In and Out, both In with inversion and out or d - isabling both. - Refer to definition of GPIO_DIRECTION for supported settings. - */ - u32 Direction : 5; - /* - Output State - Set Pad output value. - Refer to definition of GPIO_OUTPUT_STATE for supported settings. - This setting takes place when output is enabled. - */ - u32 OutputState : 2; - /* - GPIO Interrupt Configuration - Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting is applicable only if GPIO - A is in input mode. - If GPIO is set to cause an SCI then also Gpe is enabled for this pad. - Refer to definition of GPIO_INT_CONFIG for supported settings. - */ - u32 InterruptConfig : 8; - /* - GPIO Power Configuration. - This setting controls Pad Reset Configuration and Power Rail Type. - Refer to definition of GPIO_RESET_CONFIG for supported settings. - */ - u32 PowerConfig : 4; - /* - GPIO Electrical Configuration - This setting controls pads termination and voltage tolerance. - Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. - */ - u32 ElectricalConfig : 7; - /* - GPIO Lock Configuration - This setting controls pads lock. - Refer to definition of GPIO_LOCK_CONFIG for supported settings. - */ - u32 LockConfig : 3; - /* - Additional GPIO configuration - Refer to definition of GPIO_OTHER_CONFIG for supported settings. - */ - u32 OtherSettings : 2; - u32 RsvdBits : 27; -} GPIO_CONFIG; - -typedef struct { - GPIO_PAD GpioPad; - GPIO_CONFIG GpioConfig; -} GPIO_INIT_CONFIG; - -typedef enum { - GpioHardwareDefault = 0x0 -} GPIO_HARDWARE_DEFAULT; - -/* GPIO Pad Mode */ -typedef enum { - GpioPadModeGpio = 0x1, - GpioPadModeNative1 = 0x3, - GpioPadModeNative2 = 0x5, - GpioPadModeNative3 = 0x7, - GpioPadModeNative4 = 0x9, -} GPIO_PAD_MODE; - -/* Host Software Pad Ownership modes */ -typedef enum { - GpioHostOwnDefault = 0x0, /* Leave ownership value unmodified */ - GpioHostOwnAcpi = 0x1, /* Set HOST ownership to ACPI */ - GpioHostOwnGpio = 0x3 /* Set HOST ownership to GPIO */ -} GPIO_HOSTSW_OWN; - -/* GPIO Direction */ -typedef enum { - GpioDirDefault = 0x0, /* Leave pad direction setting unmodified */ - GpioDirInOut = (0x1 | (0x1 << 3)), /* Set pad for both output and input */ - GpioDirInInvOut = (0x1 | (0x3 << 3)), /* Set pad for both output and input with inversion */ - GpioDirIn = (0x3 | (0x1 << 3)), /* Set pad for input only */ - GpioDirInInv = (0x3 | (0x3 << 3)), /* Set pad for input with inversion */ - GpioDirOut = 0x5, /* Set pad for output only */ - GpioDirNone = 0x7 /* Disable both output and input */ -} GPIO_DIRECTION; - -/* GPIO Output State */ -typedef enum { - GpioOutDefault = 0x0, - GpioOutLow = 0x1, - GpioOutHigh = 0x3 -} GPIO_OUTPUT_STATE; - -/* - * GPIO interrupt configuration - * This setting is applicable only if GPIO is in input mode. - * GPIO_INT_CONFIG allows to choose which interrupt is generted - * (IOxAPIC/SCI/SMI/NMI) and how it is triggered (edge or level). - * Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to - * GpioIntBothEdgecan to describe an interrupt e.g. GpioIntApic | GpioIntLevel - * If GPIO is set to cause an SCI then also Gpe is enabled for this pad. - * Not all GPIO are capable of generating an SMI or NMI interrupt - */ -typedef enum { - GpioIntDefault = 0x0, /* Leave value of interrupt routing unmodified */ - GpioIntDis = 0x1, /* Disable IOxAPIC/SCI/SMI/NMI interrupt generation */ - GpioIntNmi = 0x3, /* Enable NMI interrupt only */ - GpioIntSmi = 0x5, /* Enable SMI interrupt only */ - GpioIntSci = 0x9, /* Enable SCI interrupt only */ - GpioIntApic = 0x11, /* Enable IOxAPIC interrupt only */ - GpioIntLevel = (0x1 << 5), /* Set interrupt as level triggered */ - GpioIntEdge = (0x3 << 5), /* Set interrupt as edge triggered */ - GpioIntLvlEdgDis = (0x5 << 5), /* Disable interrupt trigger */ - GpioIntBothEdge = (0x7 << 5) /* Set interrupt as both edge triggered */ -} GPIO_INT_CONFIG; - -/* - * GPIO Power Configuration - * GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified - * Pad Register fields). - */ -typedef enum { - GpioResetDefault = 0x0, /* Leave value of pad reset unmodified */ - GpioResetPwrGood = 0x1, /* Powergood reset */ - GpioResetDeep = 0x3, /* Deep GPIO Reset */ - GpioResetNormal = 0x5, /* GPIO Reset */ - GpioResetResume = 0x7 /* Resume Reset */ -} GPIO_RESET_CONFIG; - -/* - * GPIO Electrical Configuration - * Set GPIO termination and Pad Tolerance (applicable only for some pads) - * Field from GpioTermDefault to GpioTermNative can be OR'ed with - * GpioTolerance1v8. - */ -typedef enum { - GpioTermDefault = 0x0, /* Leave termination setting unmodified */ - GpioTermNone = 0x1, /* none */ - GpioTermWpd5K = 0x5, /* 5kOhm weak pull-down */ - GpioTermWpd20K = 0x9, /* 20kOhm weak pull-down */ - GpioTermWpu1K = 0x13, /* 1kOhm weak pull-up */ - GpioTermWpu2K = 0x17, /* 2kOhm weak pull-up */ - GpioTermWpu5K = 0x15, /* 5kOhm weak pull-up */ - GpioTermWpu20K = 0x19, /* 20kOhm weak pull-up */ - GpioTermWpu1K2K = 0x1B, /* 1kOhm & 2kOhm weak pull-up */ - GpioTermNative = 0x1F, /* Native function for pads termination */ - GpioNoTolerance1v8 = (0x1 << 5), /* Disable 1.8V pad tolerance */ - GpioTolerance1v8 = (0x3 << 5) /* Enable 1.8V pad tolerance */ -} GPIO_ELECTRICAL_CONFIG; - -/* - * GPIO LockConfiguration - * Set GPIO configuration lock and output state lock - * GpioLockPadConfig and GpioLockOutputState can be OR'ed - */ -typedef enum { - GpioLockDefault = 0x0, /* Leave lock setting unmodified */ - GpioPadConfigLock = 0x3, /* Lock Pad Configuration */ - GpioOutputStateLock = 0x5 /* Lock GPIO pad output value */ -} GPIO_LOCK_CONFIG; - -/* - * Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often - * settings and for future extensions Supported settings: - * - RX raw override to '1' - allows to override input value to '1' - * This is applicable only if in input mode (both in GPIO and native usage) - * The override takes place at the internal pad state directly from buffer - * and before the RXINV. - */ -typedef enum { - GpioRxRaw1Default = 0x0, /* Use default input override value */ - GpioRxRaw1Dis = 0x1, /* Don't override input */ - GpioRxRaw1En = 0x3 /* Override input to '1' */ -} GPIO_OTHER_CONFIG; - -/* - * LP GPIO pins: Use below for functions from PCH GPIO Lib which - * require GpioPad as argument. Encoding used here - * has all information required by library functions - */ -#define GPIO_LP_GPP_A0 0x02000000 -#define GPIO_LP_GPP_A1 0x02000001 -#define GPIO_LP_GPP_A2 0x02000002 -#define GPIO_LP_GPP_A3 0x02000003 -#define GPIO_LP_GPP_A4 0x02000004 -#define GPIO_LP_GPP_A5 0x02000005 -#define GPIO_LP_GPP_A6 0x02000006 -#define GPIO_LP_GPP_A7 0x02000007 -#define GPIO_LP_GPP_A8 0x02000008 -#define GPIO_LP_GPP_A9 0x02000009 -#define GPIO_LP_GPP_A10 0x0200000A -#define GPIO_LP_GPP_A11 0x0200000B -#define GPIO_LP_GPP_A12 0x0200000C -#define GPIO_LP_GPP_A13 0x0200000D -#define GPIO_LP_GPP_A14 0x0200000E -#define GPIO_LP_GPP_A15 0x0200000F -#define GPIO_LP_GPP_A16 0x02000010 -#define GPIO_LP_GPP_A17 0x02000011 -#define GPIO_LP_GPP_A18 0x02000012 -#define GPIO_LP_GPP_A19 0x02000013 -#define GPIO_LP_GPP_A20 0x02000014 -#define GPIO_LP_GPP_A21 0x02000015 -#define GPIO_LP_GPP_A22 0x02000016 -#define GPIO_LP_GPP_A23 0x02000017 -#define GPIO_LP_GPP_B0 0x02010000 -#define GPIO_LP_GPP_B1 0x02010001 -#define GPIO_LP_GPP_B2 0x02010002 -#define GPIO_LP_GPP_B3 0x02010003 -#define GPIO_LP_GPP_B4 0x02010004 -#define GPIO_LP_GPP_B5 0x02010005 -#define GPIO_LP_GPP_B6 0x02010006 -#define GPIO_LP_GPP_B7 0x02010007 -#define GPIO_LP_GPP_B8 0x02010008 -#define GPIO_LP_GPP_B9 0x02010009 -#define GPIO_LP_GPP_B10 0x0201000A -#define GPIO_LP_GPP_B11 0x0201000B -#define GPIO_LP_GPP_B12 0x0201000C -#define GPIO_LP_GPP_B13 0x0201000D -#define GPIO_LP_GPP_B14 0x0201000E -#define GPIO_LP_GPP_B15 0x0201000F -#define GPIO_LP_GPP_B16 0x02010010 -#define GPIO_LP_GPP_B17 0x02010011 -#define GPIO_LP_GPP_B18 0x02010012 -#define GPIO_LP_GPP_B19 0x02010013 -#define GPIO_LP_GPP_B20 0x02010014 -#define GPIO_LP_GPP_B21 0x02010015 -#define GPIO_LP_GPP_B22 0x02010016 -#define GPIO_LP_GPP_B23 0x02010017 -#define GPIO_LP_GPP_C0 0x02020000 -#define GPIO_LP_GPP_C1 0x02020001 -#define GPIO_LP_GPP_C2 0x02020002 -#define GPIO_LP_GPP_C3 0x02020003 -#define GPIO_LP_GPP_C4 0x02020004 -#define GPIO_LP_GPP_C5 0x02020005 -#define GPIO_LP_GPP_C6 0x02020006 -#define GPIO_LP_GPP_C7 0x02020007 -#define GPIO_LP_GPP_C8 0x02020008 -#define GPIO_LP_GPP_C9 0x02020009 -#define GPIO_LP_GPP_C10 0x0202000A -#define GPIO_LP_GPP_C11 0x0202000B -#define GPIO_LP_GPP_C12 0x0202000C -#define GPIO_LP_GPP_C13 0x0202000D -#define GPIO_LP_GPP_C14 0x0202000E -#define GPIO_LP_GPP_C15 0x0202000F -#define GPIO_LP_GPP_C16 0x02020010 -#define GPIO_LP_GPP_C17 0x02020011 -#define GPIO_LP_GPP_C18 0x02020012 -#define GPIO_LP_GPP_C19 0x02020013 -#define GPIO_LP_GPP_C20 0x02020014 -#define GPIO_LP_GPP_C21 0x02020015 -#define GPIO_LP_GPP_C22 0x02020016 -#define GPIO_LP_GPP_C23 0x02020017 -#define GPIO_LP_GPP_D0 0x02030000 -#define GPIO_LP_GPP_D1 0x02030001 -#define GPIO_LP_GPP_D2 0x02030002 -#define GPIO_LP_GPP_D3 0x02030003 -#define GPIO_LP_GPP_D4 0x02030004 -#define GPIO_LP_GPP_D5 0x02030005 -#define GPIO_LP_GPP_D6 0x02030006 -#define GPIO_LP_GPP_D7 0x02030007 -#define GPIO_LP_GPP_D8 0x02030008 -#define GPIO_LP_GPP_D9 0x02030009 -#define GPIO_LP_GPP_D10 0x0203000A -#define GPIO_LP_GPP_D11 0x0203000B -#define GPIO_LP_GPP_D12 0x0203000C -#define GPIO_LP_GPP_D13 0x0203000D -#define GPIO_LP_GPP_D14 0x0203000E -#define GPIO_LP_GPP_D15 0x0203000F -#define GPIO_LP_GPP_D16 0x02030010 -#define GPIO_LP_GPP_D17 0x02030011 -#define GPIO_LP_GPP_D18 0x02030012 -#define GPIO_LP_GPP_D19 0x02030013 -#define GPIO_LP_GPP_D20 0x02030014 -#define GPIO_LP_GPP_D21 0x02030015 -#define GPIO_LP_GPP_D22 0x02030016 -#define GPIO_LP_GPP_D23 0x02030017 -#define GPIO_LP_GPP_E0 0x02040000 -#define GPIO_LP_GPP_E1 0x02040001 -#define GPIO_LP_GPP_E2 0x02040002 -#define GPIO_LP_GPP_E3 0x02040003 -#define GPIO_LP_GPP_E4 0x02040004 -#define GPIO_LP_GPP_E5 0x02040005 -#define GPIO_LP_GPP_E6 0x02040006 -#define GPIO_LP_GPP_E7 0x02040007 -#define GPIO_LP_GPP_E8 0x02040008 -#define GPIO_LP_GPP_E9 0x02040009 -#define GPIO_LP_GPP_E10 0x0204000A -#define GPIO_LP_GPP_E11 0x0204000B -#define GPIO_LP_GPP_E12 0x0204000C -#define GPIO_LP_GPP_E13 0x0204000D -#define GPIO_LP_GPP_E14 0x0204000E -#define GPIO_LP_GPP_E15 0x0204000F -#define GPIO_LP_GPP_E16 0x02040010 -#define GPIO_LP_GPP_E17 0x02040011 -#define GPIO_LP_GPP_E18 0x02040012 -#define GPIO_LP_GPP_E19 0x02040013 -#define GPIO_LP_GPP_E20 0x02040014 -#define GPIO_LP_GPP_E21 0x02040015 -#define GPIO_LP_GPP_E22 0x02040016 -#define GPIO_LP_GPP_E23 0x02040017 -#define GPIO_LP_GPP_F0 0x02050000 -#define GPIO_LP_GPP_F1 0x02050001 -#define GPIO_LP_GPP_F2 0x02050002 -#define GPIO_LP_GPP_F3 0x02050003 -#define GPIO_LP_GPP_F4 0x02050004 -#define GPIO_LP_GPP_F5 0x02050005 -#define GPIO_LP_GPP_F6 0x02050006 -#define GPIO_LP_GPP_F7 0x02050007 -#define GPIO_LP_GPP_F8 0x02050008 -#define GPIO_LP_GPP_F9 0x02050009 -#define GPIO_LP_GPP_F10 0x0205000A -#define GPIO_LP_GPP_F11 0x0205000B -#define GPIO_LP_GPP_F12 0x0205000C -#define GPIO_LP_GPP_F13 0x0205000D -#define GPIO_LP_GPP_F14 0x0205000E -#define GPIO_LP_GPP_F15 0x0205000F -#define GPIO_LP_GPP_F16 0x02050010 -#define GPIO_LP_GPP_F17 0x02050011 -#define GPIO_LP_GPP_F18 0x02050012 -#define GPIO_LP_GPP_F19 0x02050013 -#define GPIO_LP_GPP_F20 0x02050014 -#define GPIO_LP_GPP_F21 0x02050015 -#define GPIO_LP_GPP_F22 0x02050016 -#define GPIO_LP_GPP_F23 0x02050017 -#define GPIO_LP_GPP_G0 0x02060000 -#define GPIO_LP_GPP_G1 0x02060001 -#define GPIO_LP_GPP_G2 0x02060002 -#define GPIO_LP_GPP_G3 0x02060003 -#define GPIO_LP_GPP_G4 0x02060004 -#define GPIO_LP_GPP_G5 0x02060005 -#define GPIO_LP_GPP_G6 0x02060006 -#define GPIO_LP_GPP_G7 0x02060007 -#define GPIO_LP_GPD0 0x02070000 -#define GPIO_LP_GPD1 0x02070001 -#define GPIO_LP_GPD2 0x02070002 -#define GPIO_LP_GPD3 0x02070003 -#define GPIO_LP_GPD4 0x02070004 -#define GPIO_LP_GPD5 0x02070005 -#define GPIO_LP_GPD6 0x02070006 -#define GPIO_LP_GPD7 0x02070007 -#define GPIO_LP_GPD8 0x02070008 -#define GPIO_LP_GPD9 0x02070009 -#define GPIO_LP_GPD10 0x0207000A -#define GPIO_LP_GPD11 0x0207000B - -#define END_OF_GPIO_TABLE 0xFFFFFFFF #endif diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h new file mode 100644 index 0000000000..61d80bdffc --- /dev/null +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -0,0 +1,479 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _SOC_GPIO_DEFS_H_ +#define _SOC_GPIO_DEFS_H_ + +/* + * GPIOs are ordered monotonically increasing to match ACPI/OS driver. + */ + +/* Group A */ +#define GPP_A0 0 +#define GPP_A1 1 +#define GPP_A2 2 +#define GPP_A3 3 +#define GPP_A4 4 +#define GPP_A5 5 +#define GPP_A6 6 +#define GPP_A7 7 +#define GPP_A8 8 +#define GPP_A9 9 +#define GPP_A10 10 +#define GPP_A11 11 +#define GPP_A12 12 +#define GPP_A13 13 +#define GPP_A14 14 +#define GPP_A15 15 +#define GPP_A16 16 +#define GPP_A17 17 +#define GPP_A18 18 +#define GPP_A19 19 +#define GPP_A20 20 +#define GPP_A21 21 +#define GPP_A22 22 +#define GPP_A23 23 +/* Group B */ +#define GPP_B0 24 +#define GPP_B1 25 +#define GPP_B2 26 +#define GPP_B3 27 +#define GPP_B4 28 +#define GPP_B5 29 +#define GPP_B6 30 +#define GPP_B7 31 +#define GPP_B8 32 +#define GPP_B9 33 +#define GPP_B10 34 +#define GPP_B11 35 +#define GPP_B12 36 +#define GPP_B13 37 +#define GPP_B14 38 +#define GPP_B15 39 +#define GPP_B16 40 +#define GPP_B17 41 +#define GPP_B18 42 +#define GPP_B19 43 +#define GPP_B20 44 +#define GPP_B21 45 +#define GPP_B22 46 +#define GPP_B23 47 +/* Group C */ +#define GPP_C0 48 +#define GPP_C1 49 +#define GPP_C2 50 +#define GPP_C3 51 +#define GPP_C4 52 +#define GPP_C5 53 +#define GPP_C6 54 +#define GPP_C7 55 +#define GPP_C8 56 +#define GPP_C9 57 +#define GPP_C10 58 +#define GPP_C11 59 +#define GPP_C12 60 +#define GPP_C13 61 +#define GPP_C14 62 +#define GPP_C15 63 +#define GPP_C16 64 +#define GPP_C17 65 +#define GPP_C18 66 +#define GPP_C19 67 +#define GPP_C20 68 +#define GPP_C21 69 +#define GPP_C22 70 +#define GPP_C23 71 +/* Group D */ +#define GPP_D0 72 +#define GPP_D1 73 +#define GPP_D2 74 +#define GPP_D3 75 +#define GPP_D4 76 +#define GPP_D5 77 +#define GPP_D6 78 +#define GPP_D7 79 +#define GPP_D8 80 +#define GPP_D9 81 +#define GPP_D10 82 +#define GPP_D11 83 +#define GPP_D12 84 +#define GPP_D13 85 +#define GPP_D14 86 +#define GPP_D15 87 +#define GPP_D16 88 +#define GPP_D17 89 +#define GPP_D18 90 +#define GPP_D19 91 +#define GPP_D20 92 +#define GPP_D21 93 +#define GPP_D22 94 +#define GPP_D23 95 +/* Group E */ +#define GPP_E0 96 +#define GPP_E1 97 +#define GPP_E2 98 +#define GPP_E3 99 +#define GPP_E4 100 +#define GPP_E5 101 +#define GPP_E6 102 +#define GPP_E7 103 +#define GPP_E8 104 +#define GPP_E9 105 +#define GPP_E10 106 +#define GPP_E11 107 +#define GPP_E12 108 +#define GPP_E13 109 +#define GPP_E14 110 +#define GPP_E15 111 +#define GPP_E16 112 +#define GPP_E17 113 +#define GPP_E18 114 +#define GPP_E19 115 +#define GPP_E20 116 +#define GPP_E21 117 +#define GPP_E22 118 +#define GPP_E23 119 +/* Group F */ +#define GPP_F0 120 +#define GPP_F1 121 +#define GPP_F2 122 +#define GPP_F3 123 +#define GPP_F4 124 +#define GPP_F5 125 +#define GPP_F6 126 +#define GPP_F7 127 +#define GPP_F8 128 +#define GPP_F9 129 +#define GPP_F10 130 +#define GPP_F11 131 +#define GPP_F12 132 +#define GPP_F13 133 +#define GPP_F14 134 +#define GPP_F15 135 +#define GPP_F16 136 +#define GPP_F17 137 +#define GPP_F18 138 +#define GPP_F19 139 +#define GPP_F20 140 +#define GPP_F21 141 +#define GPP_F22 142 +#define GPP_F23 143 +/* Group G */ +#define GPP_G0 144 +#define GPP_G1 145 +#define GPP_G2 146 +#define GPP_G3 147 +#define GPP_G4 148 +#define GPP_G5 149 +#define GPP_G6 150 +#define GPP_G7 151 +/* Group GPD */ +#define GPD0 152 +#define GPD1 153 +#define GPD2 154 +#define GPD3 155 +#define GPD4 156 +#define GPD5 157 +#define GPD6 158 +#define GPD7 159 +#define GPD8 160 +#define GPD9 161 +#define GPD10 162 +#define GPD11 163 + +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group A */ +#define GPP_A0_IRQ 0x18 +#define GPP_A1_IRQ 0x19 +#define GPP_A2_IRQ 0x1a +#define GPP_A3_IRQ 0x1b +#define GPP_A4_IRQ 0x1c +#define GPP_A5_IRQ 0x1d +#define GPP_A6_IRQ 0x1e +#define GPP_A7_IRQ 0x1f +#define GPP_A8_IRQ 0x20 +#define GPP_A9_IRQ 0x21 +#define GPP_A10_IRQ 0x22 +#define GPP_A11_IRQ 0x23 +#define GPP_A12_IRQ 0x24 +#define GPP_A13_IRQ 0x25 +#define GPP_A14_IRQ 0x26 +#define GPP_A15_IRQ 0x27 +#define GPP_A16_IRQ 0x28 +#define GPP_A17_IRQ 0x29 +#define GPP_A18_IRQ 0x2a +#define GPP_A19_IRQ 0x2b +#define GPP_A20_IRQ 0x2c +#define GPP_A21_IRQ 0x2d +#define GPP_A22_IRQ 0x2e +#define GPP_A23_IRQ 0x2f +/* Group B */ +#define GPP_B0_IRQ 0x30 +#define GPP_B1_IRQ 0x31 +#define GPP_B2_IRQ 0x32 +#define GPP_B3_IRQ 0x33 +#define GPP_B4_IRQ 0x34 +#define GPP_B5_IRQ 0x35 +#define GPP_B6_IRQ 0x36 +#define GPP_B7_IRQ 0x37 +#define GPP_B8_IRQ 0x38 +#define GPP_B9_IRQ 0x39 +#define GPP_B10_IRQ 0x3a +#define GPP_B11_IRQ 0x3b +#define GPP_B12_IRQ 0x3c +#define GPP_B13_IRQ 0x3d +#define GPP_B14_IRQ 0x3e +#define GPP_B15_IRQ 0x3f +#define GPP_B16_IRQ 0x40 +#define GPP_B17_IRQ 0x41 +#define GPP_B18_IRQ 0x42 +#define GPP_B19_IRQ 0x43 +#define GPP_B20_IRQ 0x44 +#define GPP_B21_IRQ 0x45 +#define GPP_B22_IRQ 0x46 +#define GPP_B23_IRQ 0x47 +/* Group C */ +#define GPP_C0_IRQ 0x48 +#define GPP_C1_IRQ 0x49 +#define GPP_C2_IRQ 0x4a +#define GPP_C3_IRQ 0x4b +#define GPP_C4_IRQ 0x4c +#define GPP_C5_IRQ 0x4d +#define GPP_C6_IRQ 0x4e +#define GPP_C7_IRQ 0x4f +#define GPP_C8_IRQ 0x50 +#define GPP_C9_IRQ 0x51 +#define GPP_C10_IRQ 0x52 +#define GPP_C11_IRQ 0x53 +#define GPP_C12_IRQ 0x54 +#define GPP_C13_IRQ 0x55 +#define GPP_C14_IRQ 0x56 +#define GPP_C15_IRQ 0x57 +#define GPP_C16_IRQ 0x58 +#define GPP_C17_IRQ 0x59 +#define GPP_C18_IRQ 0x5a +#define GPP_C19_IRQ 0x5b +#define GPP_C20_IRQ 0x5c +#define GPP_C21_IRQ 0x5d +#define GPP_C22_IRQ 0x5e +#define GPP_C23_IRQ 0x5f +/* Group D */ +#define GPP_D0_IRQ 0x60 +#define GPP_D1_IRQ 0x61 +#define GPP_D2_IRQ 0x62 +#define GPP_D3_IRQ 0x63 +#define GPP_D4_IRQ 0x64 +#define GPP_D5_IRQ 0x65 +#define GPP_D6_IRQ 0x66 +#define GPP_D7_IRQ 0x67 +#define GPP_D8_IRQ 0x68 +#define GPP_D9_IRQ 0x69 +#define GPP_D10_IRQ 0x6a +#define GPP_D11_IRQ 0x6b +#define GPP_D12_IRQ 0x6c +#define GPP_D13_IRQ 0x6d +#define GPP_D14_IRQ 0x6e +#define GPP_D15_IRQ 0x6f +#define GPP_D16_IRQ 0x70 +#define GPP_D17_IRQ 0x71 +#define GPP_D18_IRQ 0x72 +#define GPP_D19_IRQ 0x73 +#define GPP_D20_IRQ 0x74 +#define GPP_D21_IRQ 0x75 +#define GPP_D22_IRQ 0x76 +#define GPP_D23_IRQ 0x77 +/* Group E */ +#define GPP_E0_IRQ 0x18 +#define GPP_E1_IRQ 0x19 +#define GPP_E2_IRQ 0x1a +#define GPP_E3_IRQ 0x1b +#define GPP_E4_IRQ 0x1c +#define GPP_E5_IRQ 0x1d +#define GPP_E6_IRQ 0x1e +#define GPP_E7_IRQ 0x1f +#define GPP_E8_IRQ 0x20 +#define GPP_E9_IRQ 0x21 +#define GPP_E10_IRQ 0x22 +#define GPP_E11_IRQ 0x23 +#define GPP_E12_IRQ 0x24 +#define GPP_E13_IRQ 0x25 +#define GPP_E14_IRQ 0x26 +#define GPP_E15_IRQ 0x27 +#define GPP_E16_IRQ 0x28 +#define GPP_E17_IRQ 0x29 +#define GPP_E18_IRQ 0x2a +#define GPP_E19_IRQ 0x2b +#define GPP_E20_IRQ 0x2c +#define GPP_E21_IRQ 0x2d +#define GPP_E22_IRQ 0x2e +#define GPP_E23_IRQ 0x2f +/* Group F */ +#define GPP_F0_IRQ 0x30 +#define GPP_F1_IRQ 0x31 +#define GPP_F2_IRQ 0x32 +#define GPP_F3_IRQ 0x33 +#define GPP_F4_IRQ 0x34 +#define GPP_F5_IRQ 0x35 +#define GPP_F6_IRQ 0x36 +#define GPP_F7_IRQ 0x37 +#define GPP_F8_IRQ 0x38 +#define GPP_F9_IRQ 0x39 +#define GPP_F10_IRQ 0x3a +#define GPP_F11_IRQ 0x3b +#define GPP_F12_IRQ 0x3c +#define GPP_F13_IRQ 0x3d +#define GPP_F14_IRQ 0x3e +#define GPP_F15_IRQ 0x3f +#define GPP_F16_IRQ 0x40 +#define GPP_F17_IRQ 0x41 +#define GPP_F18_IRQ 0x42 +#define GPP_F19_IRQ 0x43 +#define GPP_F20_IRQ 0x44 +#define GPP_F21_IRQ 0x45 +#define GPP_F22_IRQ 0x46 +#define GPP_F23_IRQ 0x47 +/* Group G */ +#define GPP_G0_IRQ 0x48 +#define GPP_G1_IRQ 0x49 +#define GPP_G2_IRQ 0x4a +#define GPP_G3_IRQ 0x4b +#define GPP_G4_IRQ 0x4c +#define GPP_G5_IRQ 0x4d +#define GPP_G6_IRQ 0x4e +#define GPP_G7_IRQ 0x4f +/* Group GPD */ +#define GPD0_IRQ 0x50 +#define GPD1_IRQ 0x51 +#define GPD2_IRQ 0x52 +#define GPD3_IRQ 0x53 +#define GPD4_IRQ 0x54 +#define GPD5_IRQ 0x55 +#define GPD6_IRQ 0x56 +#define GPD7_IRQ 0x57 +#define GPD8_IRQ 0x58 +#define GPD9_IRQ 0x59 +#define GPD10_IRQ 0x5a +#define GPD11_IRQ 0x5b + +/* Register defines. */ +#define PAD_OWN_REG_OFFSET 0x20 +#define PAD_OWN_PADS_PER 8 +#define PAD_OWN_WIDTH_PER 4 +#define PAD_OWN_MASK 0x03 +#define PAD_OWN_HOST 0x00 +#define PAD_OWN_ME 0x01 +#define PAD_OWN_ISH 0x02 +#define HOSTSW_OWN_REG_OFFSET 0xd0 +#define HOSTSW_OWN_PADS_PER 24 +#define HOSTSW_OWN_ACPI 0 +#define HOSTSW_OWN_GPIO 1 +#define PAD_CFG_DW_OFFSET 0x400 + /* PADRSTCFG - when to reset the pad config */ +#define PADRSTCFG_SHIFT 30 +#define PADRSTCFG_MASK 0x3 +#define PADRSTCFG_DSW_PWROK 0 +#define PADRSTCFG_DEEP 1 +#define PADRSTCFG_PLTRST 2 +#define PADRSTCFG_RSMRST 3 + /* RXPADSTSEL - raw signal or internal state */ +#define RXPADSTSEL_SHIFT 29 +#define RXPADSTSEL_MASK 0x1 +#define RXPADSTSEL_RAW 0 +#define RXPADSTSEL_INTERNAL 1 + /* RXRAW1 - drive 1 instead instead of pad value */ +#define RXRAW1_SHIFT 28 +#define RXRAW1_MASK 0x1 +#define RXRAW1_NO 0 +#define RXRAW1_YES 1 + /* RXEVCFG - Interrupt and wake types */ +#define RXEVCFG_SHIFT 25 +#define RXEVCFG_MASK 0x3 +#define RXEVCFG_LEVEL 0 +#define RXEVCFG_EDGE 1 +#define RXEVCFG_DRIVE0 2 + /* PREGFRXSEL - use filtering on Rx pad */ +#define PREGFRXSEL_SHIFT 24 +#define PREGFRXSEL_MASK 0x1 +#define PREGFRXSEL_NO 0 +#define PREGFRXSEL_YES 1 + /* RXINV - invert signal to SMI, SCI, NMI, or IRQ routing. */ +#define RXINV_SHIFT 23 +#define RXINV_MASK 0x1 +#define RXINV_NO 0 +#define RXINV_YES 1 + /* GPIROUTIOXAPIC - route to io-xapic or not */ +#define GPIROUTIOXAPIC_SHIFT 20 +#define GPIROUTIOXAPIC_MASK 0x1 +#define GPIROUTIOXAPIC_NO 0 +#define GPIROUTIOXAPIC_YES 1 + /* GPIROUTSCI - route to SCI */ +#define GPIROUTSCI_SHIFT 19 +#define GPIROUTSCI_MASK 0x1 +#define GPIROUTSCI_NO 0 +#define GPIROUTSCI_YES 1 + /* GPIROUTSMI - route to SMI */ +#define GPIROUTSMI_SHIFT 18 +#define GPIROUTSMI_MASK 0x1 +#define GPIROUTSMI_NO 0 +#define GPIROUTSMI_YES 1 + /* GPIROUTNMI - route to NMI */ +#define GPIROUTNMI_SHIFT 17 +#define GPIROUTNMI_MASK 0x1 +#define GPIROUTNMI_NO 0 +#define GPIROUTNMI_YES 1 + /* PMODE - mode of pad */ +#define PMODE_SHIFT 10 +#define PMODE_MASK 0x3 +#define PMODE_GPIO 0 +#define PMODE_NF1 1 +#define PMODE_NF2 2 +#define PMODE_NF3 3 + /* GPIORXDIS - Disable Rx */ +#define GPIORXDIS_SHIFT 9 +#define GPIORXDIS_MASK 0x1 +#define GPIORXDIS_NO 0 +#define GPIORXDIS_YES 1 + /* GPIOTXDIS - Disable Tx */ +#define GPIOTXDIS_SHIFT 8 +#define GPIOTXDIS_MASK 0x1 +#define GPIOTXDIS_NO 0 +#define GPIOTXDIS_YES 1 + /* GPIORXSTATE - Internal state after glitch filter */ +#define GPIORXSTATE_SHIFT 1 +#define GPIORXSTATE_MASK 0x1 + /* GPIOTXSTATE - Drive value onto pad */ +#define GPIOTXSTATE_SHIFT 0 +#define GPIOTXSTATE_MASK 0x1 +#define PAD_CFG_DW_OFFSET 0x400 + /* TERM - termination control */ +#define PAD_TERM_SHIFT 10 +#define PAD_TERM_MASK 0xf +#define PAD_TERM_NONE 0 +#define PAD_TERM_5K_PD 2 +#define PAD_TERM_1K_PU 9 +#define PAD_TERM_2K_PU 11 +#define PAD_TERM_5K_PU 10 +#define PAD_TERM_20K_PU 12 +#define PAD_TERM_667_PU 13 +#define PAD_TERM_NATIVE 15 + +#endif /* _SOC_GPIO_DEFS_H_ */ diff --git a/src/soc/intel/skylake/include/soc/gpio_fsp.h b/src/soc/intel/skylake/include/soc/gpio_fsp.h new file mode 100644 index 0000000000..cedbf82cb1 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/gpio_fsp.h @@ -0,0 +1,512 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _SOC_GPIO_FSP_H_ +#define _SOC_GPIO_FSP_H_ + +#include + +/* + * GPP_Ax to GPP_Gx; + * where x=24 [between GPIO Community A to F] + * = 7 [only for GPIO Community G] + */ +#define MAX_GPIO_NUMBER 151 /* zero based */ +#define GPIO_LIST_END 0xffffffff + +/* + * Skylake LP GPIO PIN to Pad Mapping + */ +#define GPIO_LP_GROUP_A 0x0 +#define GPIO_LP_GROUP_B 0x1 +#define GPIO_LP_GROUP_C 0x2 +#define GPIO_LP_GROUP_D 0x3 +#define GPIO_LP_GROUP_E 0x4 +#define GPIO_LP_GROUP_F 0x5 +#define GPIO_LP_GROUP_G 0x6 + +#define GPIO_LP_GROUP_GPP_A 0x0200 +#define GPIO_LP_GROUP_GPP_B 0x0201 +#define GPIO_LP_GROUP_GPP_C 0x0202 +#define GPIO_LP_GROUP_GPP_D 0x0203 +#define GPIO_LP_GROUP_GPP_E 0x0204 +#define GPIO_LP_GROUP_GPP_F 0x0205 +#define GPIO_LP_GROUP_GPP_G 0x0206 + +#define GPIO_GROUP_SHIFT 16 +#define MAX_GPIO_PIN_PER_GROUP 24 + +/* GPIO TX STATE */ +#define B_PCH_GPIO_TX_STATE 0x0001 +#define N_PCH_GPIO_TX_STATE 0 + +/* Interrupt number */ +#define B_PCH_GPIO_INTSEL 0x7F +#define N_PCH_GPIO_INTSEL 0 + +/* Structure for storing information about registers offset, community, + * maximal pad number, smi status and smi enable for available groups + */ +typedef struct { + u32 community; + u32 padcfgoffset; + u32 padpergroup; + u32 smistsoffset; + u32 smienoffset; +} GPIO_GROUP_INFO; + +/* + * GPIO Community 0 Registers are for GPP_A and GPP_B groups + */ +#define R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET 0x400 +#define R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET 0x4C0 +#define R_PCH_PCR_GPIO_GPP_A_SMI_STS 0x0180 +#define R_PCH_PCR_GPIO_GPP_B_SMI_STS 0x0184 +#define R_PCH_PCR_GPIO_GPP_A_SMI_EN 0x01A0 +#define R_PCH_PCR_GPIO_GPP_B_SMI_EN 0x01A4 + +/* + * GPIO Community 1 Registers are for GPP_C, GPP_D, GPP_E groups + */ +#define R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET 0x400 +#define R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET 0x4C0 +#define R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET 0x580 +#define R_PCH_PCR_GPIO_GPP_C_SMI_STS 0x0180 +#define R_PCH_PCR_GPIO_GPP_D_SMI_STS 0x0184 +#define R_PCH_PCR_GPIO_GPP_E_SMI_STS 0x0188 +#define R_PCH_PCR_GPIO_GPP_C_SMI_EN 0x01A0 +#define R_PCH_PCR_GPIO_GPP_D_SMI_EN 0x01A4 +#define R_PCH_PCR_GPIO_GPP_E_SMI_EN 0x01A8 + +/* + * GPIO Community 3 Registers are for GPP_F and GPP_G groups + */ +#define R_PCH_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x400 +#define R_PCH_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x4C0 + +/* + * GPIO Community 2 Registers are for GPP_DSW + */ +#define R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET 0x400 + +#define READ 0 +#define WRITE 1 + +/* If in GPIO_GROUP_INFO structure certain register doesn't exist + * it will have value equal to NO_REGISTER_PROPERTY + */ +#define NO_REGISTER_PROPERTY (~0u) + +#define V_PCH_GPIO_GPP_A_PAD_MAX 24 +#define V_PCH_GPIO_GPP_B_PAD_MAX 24 +#define V_PCH_GPIO_GPP_C_PAD_MAX 24 +#define V_PCH_GPIO_GPP_D_PAD_MAX 24 +#define V_PCH_GPIO_GPP_E_PAD_MAX 24 +#define V_PCH_GPIO_GPP_F_PAD_MAX 24 +#define V_PCH_GPIO_GPP_G_PAD_MAX 8 +#define V_PCH_GPIO_GPD_PAD_MAX 12 + +#define GPIO_GET_GROUP_INDEX(group) (group & 0xFF) +#define GPIO_GET_GROUP_INDEX_FROM_PAD(pad) (\ + GPIO_GET_GROUP_INDEX((pad >> 16))) +#define GPIO_GET_PAD_NUMBER(pad) (pad & 0xFFFF) + +/* Number of pins used by SerialIo controllers */ +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4 +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2 + +/* Below defines are based on GPIO_CONFIG structure fields */ +#define GPIO_CONF_PAD_MODE_MASK 0xF +#define GPIO_CONF_PAD_MODE_BIT_POS 0 + +/* GPIO Pad Mode */ +#define B_PCH_GPIO_PAD_MODE (0x1000 | 0x800 | 0x400) +#define N_PCH_GPIO_PAD_MODE 10 + +/* For any GpioPad usage in code use GPIO_PAD type*/ +typedef u32 GPIO_PAD; + +/* For any GpioGroup usage in code use GPIO_GROUP type */ +typedef u32 GPIO_GROUP; + +/* + * GPIO configuration structure used for pin programming. + * Structure contains fields that can be used to configure pad. + */ +typedef struct { + /* + Pad Mode + Pad can be set as GPIO or one of its native functions. + When in native mode setting Direction, OutputState, Interrupt is unnecessary. + Refer to definition of GPIO_PAD_MODE. + Refer to EDS for each native mode according to the pad. + */ + u32 PadMode : 4; + /* + Host Software Pad Ownership + Set pad to ACPI mode or GPIO Driver Mode. + Refer to definition of GPIO_HOSTSW_OWN. + */ + u32 HostSoftPadOwn : 2; + /* + GPIO Direction + Can choose between In, In with inversion Out, both In and Out, both In with inversion and out or d + isabling both. + Refer to definition of GPIO_DIRECTION for supported settings. + */ + u32 Direction : 5; + /* + Output State + Set Pad output value. + Refer to definition of GPIO_OUTPUT_STATE for supported settings. + This setting takes place when output is enabled. + */ + u32 OutputState : 2; + /* + GPIO Interrupt Configuration + Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting is applicable only if GPIO + A is in input mode. + If GPIO is set to cause an SCI then also Gpe is enabled for this pad. + Refer to definition of GPIO_INT_CONFIG for supported settings. + */ + u32 InterruptConfig : 8; + /* + GPIO Power Configuration. + This setting controls Pad Reset Configuration and Power Rail Type. + Refer to definition of GPIO_RESET_CONFIG for supported settings. + */ + u32 PowerConfig : 4; + /* + GPIO Electrical Configuration + This setting controls pads termination and voltage tolerance. + Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. + */ + u32 ElectricalConfig : 7; + /* + GPIO Lock Configuration + This setting controls pads lock. + Refer to definition of GPIO_LOCK_CONFIG for supported settings. + */ + u32 LockConfig : 3; + /* + Additional GPIO configuration + Refer to definition of GPIO_OTHER_CONFIG for supported settings. + */ + u32 OtherSettings : 2; + u32 RsvdBits : 27; +} GPIO_CONFIG; + +typedef struct { + GPIO_PAD GpioPad; + GPIO_CONFIG GpioConfig; +} GPIO_INIT_CONFIG; + +typedef enum { + GpioHardwareDefault = 0x0 +} GPIO_HARDWARE_DEFAULT; + +/* GPIO Pad Mode */ +typedef enum { + GpioPadModeGpio = 0x1, + GpioPadModeNative1 = 0x3, + GpioPadModeNative2 = 0x5, + GpioPadModeNative3 = 0x7, + GpioPadModeNative4 = 0x9, +} GPIO_PAD_MODE; + +/* Host Software Pad Ownership modes */ +typedef enum { + GpioHostOwnDefault = 0x0, /* Leave ownership value unmodified */ + GpioHostOwnAcpi = 0x1, /* Set HOST ownership to ACPI */ + GpioHostOwnGpio = 0x3 /* Set HOST ownership to GPIO */ +} GPIO_HOSTSW_OWN; + +/* GPIO Direction */ +typedef enum { + GpioDirDefault = 0x0, /* Leave pad direction setting unmodified */ + GpioDirInOut = (0x1 | (0x1 << 3)), /* Set pad for both output and input */ + GpioDirInInvOut = (0x1 | (0x3 << 3)), /* Set pad for both output and input with inversion */ + GpioDirIn = (0x3 | (0x1 << 3)), /* Set pad for input only */ + GpioDirInInv = (0x3 | (0x3 << 3)), /* Set pad for input with inversion */ + GpioDirOut = 0x5, /* Set pad for output only */ + GpioDirNone = 0x7 /* Disable both output and input */ +} GPIO_DIRECTION; + +/* GPIO Output State */ +typedef enum { + GpioOutDefault = 0x0, + GpioOutLow = 0x1, + GpioOutHigh = 0x3 +} GPIO_OUTPUT_STATE; + +/* + * GPIO interrupt configuration + * This setting is applicable only if GPIO is in input mode. + * GPIO_INT_CONFIG allows to choose which interrupt is generted + * (IOxAPIC/SCI/SMI/NMI) and how it is triggered (edge or level). + * Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to + * GpioIntBothEdgecan to describe an interrupt e.g. GpioIntApic | GpioIntLevel + * If GPIO is set to cause an SCI then also Gpe is enabled for this pad. + * Not all GPIO are capable of generating an SMI or NMI interrupt + */ +typedef enum { + GpioIntDefault = 0x0, /* Leave value of interrupt routing unmodified */ + GpioIntDis = 0x1, /* Disable IOxAPIC/SCI/SMI/NMI interrupt generation */ + GpioIntNmi = 0x3, /* Enable NMI interrupt only */ + GpioIntSmi = 0x5, /* Enable SMI interrupt only */ + GpioIntSci = 0x9, /* Enable SCI interrupt only */ + GpioIntApic = 0x11, /* Enable IOxAPIC interrupt only */ + GpioIntLevel = (0x1 << 5), /* Set interrupt as level triggered */ + GpioIntEdge = (0x3 << 5), /* Set interrupt as edge triggered */ + GpioIntLvlEdgDis = (0x5 << 5), /* Disable interrupt trigger */ + GpioIntBothEdge = (0x7 << 5) /* Set interrupt as both edge triggered */ +} GPIO_INT_CONFIG; + +/* + * GPIO Power Configuration + * GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified + * Pad Register fields). + */ +typedef enum { + GpioResetDefault = 0x0, /* Leave value of pad reset unmodified */ + GpioResetPwrGood = 0x1, /* Powergood reset */ + GpioResetDeep = 0x3, /* Deep GPIO Reset */ + GpioResetNormal = 0x5, /* GPIO Reset */ + GpioResetResume = 0x7 /* Resume Reset */ +} GPIO_RESET_CONFIG; + +/* + * GPIO Electrical Configuration + * Set GPIO termination and Pad Tolerance (applicable only for some pads) + * Field from GpioTermDefault to GpioTermNative can be OR'ed with + * GpioTolerance1v8. + */ +typedef enum { + GpioTermDefault = 0x0, /* Leave termination setting unmodified */ + GpioTermNone = 0x1, /* none */ + GpioTermWpd5K = 0x5, /* 5kOhm weak pull-down */ + GpioTermWpd20K = 0x9, /* 20kOhm weak pull-down */ + GpioTermWpu1K = 0x13, /* 1kOhm weak pull-up */ + GpioTermWpu2K = 0x17, /* 2kOhm weak pull-up */ + GpioTermWpu5K = 0x15, /* 5kOhm weak pull-up */ + GpioTermWpu20K = 0x19, /* 20kOhm weak pull-up */ + GpioTermWpu1K2K = 0x1B, /* 1kOhm & 2kOhm weak pull-up */ + GpioTermNative = 0x1F, /* Native function for pads termination */ + GpioNoTolerance1v8 = (0x1 << 5), /* Disable 1.8V pad tolerance */ + GpioTolerance1v8 = (0x3 << 5) /* Enable 1.8V pad tolerance */ +} GPIO_ELECTRICAL_CONFIG; + +/* + * GPIO LockConfiguration + * Set GPIO configuration lock and output state lock + * GpioLockPadConfig and GpioLockOutputState can be OR'ed + */ +typedef enum { + GpioLockDefault = 0x0, /* Leave lock setting unmodified */ + GpioPadConfigLock = 0x3, /* Lock Pad Configuration */ + GpioOutputStateLock = 0x5 /* Lock GPIO pad output value */ +} GPIO_LOCK_CONFIG; + +/* + * Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often + * settings and for future extensions Supported settings: + * - RX raw override to '1' - allows to override input value to '1' + * This is applicable only if in input mode (both in GPIO and native usage) + * The override takes place at the internal pad state directly from buffer + * and before the RXINV. + */ +typedef enum { + GpioRxRaw1Default = 0x0, /* Use default input override value */ + GpioRxRaw1Dis = 0x1, /* Don't override input */ + GpioRxRaw1En = 0x3 /* Override input to '1' */ +} GPIO_OTHER_CONFIG; + +/* + * LP GPIO pins: Use below for functions from PCH GPIO Lib which + * require GpioPad as argument. Encoding used here + * has all information required by library functions + */ +#define GPIO_LP_GPP_A0 0x02000000 +#define GPIO_LP_GPP_A1 0x02000001 +#define GPIO_LP_GPP_A2 0x02000002 +#define GPIO_LP_GPP_A3 0x02000003 +#define GPIO_LP_GPP_A4 0x02000004 +#define GPIO_LP_GPP_A5 0x02000005 +#define GPIO_LP_GPP_A6 0x02000006 +#define GPIO_LP_GPP_A7 0x02000007 +#define GPIO_LP_GPP_A8 0x02000008 +#define GPIO_LP_GPP_A9 0x02000009 +#define GPIO_LP_GPP_A10 0x0200000A +#define GPIO_LP_GPP_A11 0x0200000B +#define GPIO_LP_GPP_A12 0x0200000C +#define GPIO_LP_GPP_A13 0x0200000D +#define GPIO_LP_GPP_A14 0x0200000E +#define GPIO_LP_GPP_A15 0x0200000F +#define GPIO_LP_GPP_A16 0x02000010 +#define GPIO_LP_GPP_A17 0x02000011 +#define GPIO_LP_GPP_A18 0x02000012 +#define GPIO_LP_GPP_A19 0x02000013 +#define GPIO_LP_GPP_A20 0x02000014 +#define GPIO_LP_GPP_A21 0x02000015 +#define GPIO_LP_GPP_A22 0x02000016 +#define GPIO_LP_GPP_A23 0x02000017 +#define GPIO_LP_GPP_B0 0x02010000 +#define GPIO_LP_GPP_B1 0x02010001 +#define GPIO_LP_GPP_B2 0x02010002 +#define GPIO_LP_GPP_B3 0x02010003 +#define GPIO_LP_GPP_B4 0x02010004 +#define GPIO_LP_GPP_B5 0x02010005 +#define GPIO_LP_GPP_B6 0x02010006 +#define GPIO_LP_GPP_B7 0x02010007 +#define GPIO_LP_GPP_B8 0x02010008 +#define GPIO_LP_GPP_B9 0x02010009 +#define GPIO_LP_GPP_B10 0x0201000A +#define GPIO_LP_GPP_B11 0x0201000B +#define GPIO_LP_GPP_B12 0x0201000C +#define GPIO_LP_GPP_B13 0x0201000D +#define GPIO_LP_GPP_B14 0x0201000E +#define GPIO_LP_GPP_B15 0x0201000F +#define GPIO_LP_GPP_B16 0x02010010 +#define GPIO_LP_GPP_B17 0x02010011 +#define GPIO_LP_GPP_B18 0x02010012 +#define GPIO_LP_GPP_B19 0x02010013 +#define GPIO_LP_GPP_B20 0x02010014 +#define GPIO_LP_GPP_B21 0x02010015 +#define GPIO_LP_GPP_B22 0x02010016 +#define GPIO_LP_GPP_B23 0x02010017 +#define GPIO_LP_GPP_C0 0x02020000 +#define GPIO_LP_GPP_C1 0x02020001 +#define GPIO_LP_GPP_C2 0x02020002 +#define GPIO_LP_GPP_C3 0x02020003 +#define GPIO_LP_GPP_C4 0x02020004 +#define GPIO_LP_GPP_C5 0x02020005 +#define GPIO_LP_GPP_C6 0x02020006 +#define GPIO_LP_GPP_C7 0x02020007 +#define GPIO_LP_GPP_C8 0x02020008 +#define GPIO_LP_GPP_C9 0x02020009 +#define GPIO_LP_GPP_C10 0x0202000A +#define GPIO_LP_GPP_C11 0x0202000B +#define GPIO_LP_GPP_C12 0x0202000C +#define GPIO_LP_GPP_C13 0x0202000D +#define GPIO_LP_GPP_C14 0x0202000E +#define GPIO_LP_GPP_C15 0x0202000F +#define GPIO_LP_GPP_C16 0x02020010 +#define GPIO_LP_GPP_C17 0x02020011 +#define GPIO_LP_GPP_C18 0x02020012 +#define GPIO_LP_GPP_C19 0x02020013 +#define GPIO_LP_GPP_C20 0x02020014 +#define GPIO_LP_GPP_C21 0x02020015 +#define GPIO_LP_GPP_C22 0x02020016 +#define GPIO_LP_GPP_C23 0x02020017 +#define GPIO_LP_GPP_D0 0x02030000 +#define GPIO_LP_GPP_D1 0x02030001 +#define GPIO_LP_GPP_D2 0x02030002 +#define GPIO_LP_GPP_D3 0x02030003 +#define GPIO_LP_GPP_D4 0x02030004 +#define GPIO_LP_GPP_D5 0x02030005 +#define GPIO_LP_GPP_D6 0x02030006 +#define GPIO_LP_GPP_D7 0x02030007 +#define GPIO_LP_GPP_D8 0x02030008 +#define GPIO_LP_GPP_D9 0x02030009 +#define GPIO_LP_GPP_D10 0x0203000A +#define GPIO_LP_GPP_D11 0x0203000B +#define GPIO_LP_GPP_D12 0x0203000C +#define GPIO_LP_GPP_D13 0x0203000D +#define GPIO_LP_GPP_D14 0x0203000E +#define GPIO_LP_GPP_D15 0x0203000F +#define GPIO_LP_GPP_D16 0x02030010 +#define GPIO_LP_GPP_D17 0x02030011 +#define GPIO_LP_GPP_D18 0x02030012 +#define GPIO_LP_GPP_D19 0x02030013 +#define GPIO_LP_GPP_D20 0x02030014 +#define GPIO_LP_GPP_D21 0x02030015 +#define GPIO_LP_GPP_D22 0x02030016 +#define GPIO_LP_GPP_D23 0x02030017 +#define GPIO_LP_GPP_E0 0x02040000 +#define GPIO_LP_GPP_E1 0x02040001 +#define GPIO_LP_GPP_E2 0x02040002 +#define GPIO_LP_GPP_E3 0x02040003 +#define GPIO_LP_GPP_E4 0x02040004 +#define GPIO_LP_GPP_E5 0x02040005 +#define GPIO_LP_GPP_E6 0x02040006 +#define GPIO_LP_GPP_E7 0x02040007 +#define GPIO_LP_GPP_E8 0x02040008 +#define GPIO_LP_GPP_E9 0x02040009 +#define GPIO_LP_GPP_E10 0x0204000A +#define GPIO_LP_GPP_E11 0x0204000B +#define GPIO_LP_GPP_E12 0x0204000C +#define GPIO_LP_GPP_E13 0x0204000D +#define GPIO_LP_GPP_E14 0x0204000E +#define GPIO_LP_GPP_E15 0x0204000F +#define GPIO_LP_GPP_E16 0x02040010 +#define GPIO_LP_GPP_E17 0x02040011 +#define GPIO_LP_GPP_E18 0x02040012 +#define GPIO_LP_GPP_E19 0x02040013 +#define GPIO_LP_GPP_E20 0x02040014 +#define GPIO_LP_GPP_E21 0x02040015 +#define GPIO_LP_GPP_E22 0x02040016 +#define GPIO_LP_GPP_E23 0x02040017 +#define GPIO_LP_GPP_F0 0x02050000 +#define GPIO_LP_GPP_F1 0x02050001 +#define GPIO_LP_GPP_F2 0x02050002 +#define GPIO_LP_GPP_F3 0x02050003 +#define GPIO_LP_GPP_F4 0x02050004 +#define GPIO_LP_GPP_F5 0x02050005 +#define GPIO_LP_GPP_F6 0x02050006 +#define GPIO_LP_GPP_F7 0x02050007 +#define GPIO_LP_GPP_F8 0x02050008 +#define GPIO_LP_GPP_F9 0x02050009 +#define GPIO_LP_GPP_F10 0x0205000A +#define GPIO_LP_GPP_F11 0x0205000B +#define GPIO_LP_GPP_F12 0x0205000C +#define GPIO_LP_GPP_F13 0x0205000D +#define GPIO_LP_GPP_F14 0x0205000E +#define GPIO_LP_GPP_F15 0x0205000F +#define GPIO_LP_GPP_F16 0x02050010 +#define GPIO_LP_GPP_F17 0x02050011 +#define GPIO_LP_GPP_F18 0x02050012 +#define GPIO_LP_GPP_F19 0x02050013 +#define GPIO_LP_GPP_F20 0x02050014 +#define GPIO_LP_GPP_F21 0x02050015 +#define GPIO_LP_GPP_F22 0x02050016 +#define GPIO_LP_GPP_F23 0x02050017 +#define GPIO_LP_GPP_G0 0x02060000 +#define GPIO_LP_GPP_G1 0x02060001 +#define GPIO_LP_GPP_G2 0x02060002 +#define GPIO_LP_GPP_G3 0x02060003 +#define GPIO_LP_GPP_G4 0x02060004 +#define GPIO_LP_GPP_G5 0x02060005 +#define GPIO_LP_GPP_G6 0x02060006 +#define GPIO_LP_GPP_G7 0x02060007 +#define GPIO_LP_GPD0 0x02070000 +#define GPIO_LP_GPD1 0x02070001 +#define GPIO_LP_GPD2 0x02070002 +#define GPIO_LP_GPD3 0x02070003 +#define GPIO_LP_GPD4 0x02070004 +#define GPIO_LP_GPD5 0x02070005 +#define GPIO_LP_GPD6 0x02070006 +#define GPIO_LP_GPD7 0x02070007 +#define GPIO_LP_GPD8 0x02070008 +#define GPIO_LP_GPD9 0x02070009 +#define GPIO_LP_GPD10 0x0207000A +#define GPIO_LP_GPD11 0x0207000B + +#define END_OF_GPIO_TABLE 0xFFFFFFFF +#endif