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superio/winbond/w83627dhg: Convert romstage to generic component 

Convert the serial init to the generic romstage component and
corresponding boards using this sio.

Change-Id: I36bcf38c4351130be1ed924ecfe606336d0433f3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5588
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Edward O'Callaghan 2014-04-27 22:51:40 +10:00 committed by Kyösti Mälkki
parent dbbc136c83
commit ffe460d77a
8 changed files with 19 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/mainboard/asrock/939a785gmh/romstage.c
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@ -37,7 +37,8 @@
#include <spd.h>
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627dhg/w83627dhg.h"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs780/early_setup.c"
@ -153,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_lpc_init();
sio_init();
w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();

5
src/mainboard/kontron/kt690/romstage.c
View File

@ -38,7 +38,8 @@
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627dhg/w83627dhg.h"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
#include <cpu/amd/mtrr.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@ -89,7 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs690_dev8();
sb600_lpc_init();
w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();

5
src/mainboard/lippert/toucan-af/romstage.c
View File

@ -32,7 +32,8 @@
#include "cpu/amd/car.h"
#include "agesawrapper.h"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83627dhg/w83627dhg.h"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
#include "cpu/x86/lapic.h"
#include "drivers/pc80/i8254.c"
#include "drivers/pc80/i8259.c"
@ -69,7 +70,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb_Poweron_Init();
post_code(0x31);
w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
}

3
src/mainboard/supermicro/h8qgi/romstage.c
View File

@ -32,7 +32,8 @@
#include <nb_cimx.h>
#include <sb_cimx.h>
#include "superio/nuvoton/wpcm450/wpcm450.h"
#include "superio/winbond/w83627dhg/w83627dhg.h"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

3
src/mainboard/supermicro/h8scm/romstage.c
View File

@ -34,7 +34,8 @@
#include "src/drivers/pc80/i8254.c"
#include "src/drivers/pc80/i8259.c"
#include "superio/nuvoton/wpcm450/wpcm450.h"
#include "superio/winbond/w83627dhg/w83627dhg.h"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)

5
src/mainboard/tyan/s8226/romstage.c
View File

@ -32,7 +32,8 @@
#include <nb_cimx.h>
#include <sb_cimx.h>
#include "superio/nuvoton/wpcm450/wpcm450.h"
#include "superio/winbond/w83627dhg/w83627dhg.h"
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
#include "src/drivers/pc80/i8254.c"
#include "src/drivers/pc80/i8259.c"
@ -54,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
w83627dhg_set_clksel_48(DUMMY_DEV);
w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
sb7xx_51xx_disable_wideio(0);
post_code(0x34);

10
src/superio/winbond/w83627dhg/early_serial.c
View File

@ -37,16 +37,6 @@ void pnp_exit_ext_func_mode(device_t dev)
outb(0xaa, port);
}
void w83627dhg_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}
/**
* Select Pin 89, Pin 90 function as I2C interface SDA, SCL.
* {Pin 89, Pin 90} function can be selected as {GP33, GP32}, or

7
src/superio/winbond/w83627dhg/w83627dhg.h
View File

@ -19,8 +19,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SUPERIO_WINBOND_W83627DHG_W83627DHG_H
#define SUPERIO_WINBOND_W83627DHG_W83627DHG_H
#ifndef SUPERIO_WINBOND_W83627DHG_H
#define SUPERIO_WINBOND_W83627DHG_H
#define W83627DHG_FDC 0 /* Floppy */
#define W83627DHG_PP 1 /* Parallel port */
@ -54,8 +54,7 @@
void pnp_enter_ext_func_mode(device_t dev);
void pnp_exit_ext_func_mode(device_t dev);
void w83627dhg_enable_serial(device_t dev, u16 iobase);
void w83627dhg_enable_i2c(device_t dev);
void w83627dhg_set_clksel_48(device_t dev);
#endif
#endif /* SUPERIO_WINBOND_W83627DHG_H */