mb/google/sarien: Enable LAN clock source usage
FSP defined a special clock source usage 0x70 for PCH LAN device, update that to google sarien platform. BUG=b:120003760 TEST=Boot up into OS, ethernet able to be listed in ifconfig. Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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@ -80,7 +80,7 @@ chip soc/intel/cannonlake
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# PCIe port 9 for LAN
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register "PcieRpEnable[8]" = "1"
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register "PcieClkSrcUsage[0]" = "8"
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register "PcieClkSrcUsage[0]" = "PCIE_CLK_LAN"
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register "PcieClkSrcClkReq[0]" = "0"
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# PCIe port 10 for M.2 2230 WLAN
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@ -85,7 +85,7 @@ chip soc/intel/cannonlake
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# PCIe port 9 for LAN
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register "PcieRpEnable[8]" = "1"
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register "PcieClkSrcUsage[3]" = "8"
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register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN"
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register "PcieClkSrcClkReq[3]" = "3"
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# PCIe port 10 for M.2 2230 WLAN
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