Trivial fix up to the GPIO's connected to the IP1000 and RM4100, only set ones that are actually connected to something.
Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Joseph Smith
Joseph Smith
parent
3544c6b3b0
commit
fff297327d
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@ -1,120 +1,143 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define PME_DEV PNP_DEV(0x2e, 0x0a)
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#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
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#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
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/* Early mainboard specific GPIO setup. */
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static void mb_gpio_init(void)
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{
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device_t dev;
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uint16_t port;
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uint32_t set_gpio;
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/* Southbridge GPIOs. */
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/* Set the LPC device statically. */
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dev = PCI_DEV(0x0, 0x1f, 0x0);
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/* Set the value for GPIO base address register and enable GPIO. */
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pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
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pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
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/* Set GPIO25 to input and drive GPIO23 to high,
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* this enables the LAN controller.
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*/
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udelay(10);
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set_gpio = 0x0000ffff;
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set_gpio |= 1 << 25;
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outl(set_gpio, ICH_IO_BASE_ADDR + 0x04);
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set_gpio = 0x1b3f0000;
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set_gpio |= 1 << 23;
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outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
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/* Super I/O GPIOs. */
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dev = PME_DEV;
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port = dev >> 8;
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outb(0x55, port); /* Enter the configuration state. */
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
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pnp_set_enable(dev, 1);
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outl(0x03, PME_IO_BASE_ADDR + 0x1e); /* Force Disk Change */
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outl(0x02, PME_IO_BASE_ADDR + 0x1f); /* Floppy Data Rate */
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outl(0x81, PME_IO_BASE_ADDR + 0x20); /* UART1 FIFO */
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outl(0x00, PME_IO_BASE_ADDR + 0x21); /* UART2 FIFO */
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outl(0x00, PME_IO_BASE_ADDR + 0x22); /* Device Disable */
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outl(0x01, PME_IO_BASE_ADDR + 0x23); /* GP10 */
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outl(0x01, PME_IO_BASE_ADDR + 0x24); /* GP11 */
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outl(0x01, PME_IO_BASE_ADDR + 0x25); /* GP12 */
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outl(0x01, PME_IO_BASE_ADDR + 0x26); /* GP13 */
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outl(0x01, PME_IO_BASE_ADDR + 0x27); /* GP14 */
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outl(0x01, PME_IO_BASE_ADDR + 0x28); /* GP15 */
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outl(0x01, PME_IO_BASE_ADDR + 0x29); /* GP16 */
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outl(0x01, PME_IO_BASE_ADDR + 0x2a); /* GP17 */
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outl(0x01, PME_IO_BASE_ADDR + 0x2b); /* GP20 */
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outl(0x01, PME_IO_BASE_ADDR + 0x2c); /* GP21 */
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outl(0x01, PME_IO_BASE_ADDR + 0x2d); /* GP22 */
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outl(0x01, PME_IO_BASE_ADDR + 0x2f); /* GP24 */
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outl(0x01, PME_IO_BASE_ADDR + 0x30); /* GP25 */
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outl(0x01, PME_IO_BASE_ADDR + 0x31); /* GP26 */
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outl(0x01, PME_IO_BASE_ADDR + 0x32); /* GP27 */
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outl(0x05, PME_IO_BASE_ADDR + 0x33); /* GP30 */
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outl(0x05, PME_IO_BASE_ADDR + 0x34); /* GP31 */
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outl(0x00, PME_IO_BASE_ADDR + 0x35); /* GP32 */
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outl(0x00, PME_IO_BASE_ADDR + 0x36); /* GP33 */
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outl(0x00, PME_IO_BASE_ADDR + 0x37); /* GP34 */
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outl(0x04, PME_IO_BASE_ADDR + 0x38); /* GP35 */
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outl(0x01, PME_IO_BASE_ADDR + 0x39); /* GP36 */
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outl(0x01, PME_IO_BASE_ADDR + 0x3a); /* GP37 */
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outl(0x01, PME_IO_BASE_ADDR + 0x3b); /* GP40 */
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outl(0x01, PME_IO_BASE_ADDR + 0x3c); /* GP41 */
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outl(0x86, PME_IO_BASE_ADDR + 0x3d); /* GP42 */
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outl(0x01, PME_IO_BASE_ADDR + 0x3e); /* GP43 */
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outl(0x05, PME_IO_BASE_ADDR + 0x3f); /* GP50 */
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outl(0x05, PME_IO_BASE_ADDR + 0x40); /* GP51 */
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outl(0x05, PME_IO_BASE_ADDR + 0x41); /* GP52 */
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outl(0x04, PME_IO_BASE_ADDR + 0x42); /* GP53 */
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outl(0x05, PME_IO_BASE_ADDR + 0x43); /* GP54 */
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outl(0x04, PME_IO_BASE_ADDR + 0x44); /* GP55 */
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outl(0x05, PME_IO_BASE_ADDR + 0x45); /* GP56 */
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outl(0x04, PME_IO_BASE_ADDR + 0x46); /* GP57 */
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outl(0x01, PME_IO_BASE_ADDR + 0x47); /* GP58 */
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outl(0x01, PME_IO_BASE_ADDR + 0x48); /* GP59 */
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outl(0x00, PME_IO_BASE_ADDR + 0x4b); /* GP1 */
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outl(0x04, PME_IO_BASE_ADDR + 0x4c); /* GP2 */
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outl(0xc0, PME_IO_BASE_ADDR + 0x4d); /* GP3 */
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outl(0x00, PME_IO_BASE_ADDR + 0x4e); /* GP4 */
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outl(0x07, PME_IO_BASE_ADDR + 0x4f); /* GP5 */
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outl(0x00, PME_IO_BASE_ADDR + 0x50); /* GP6 */
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outl(0x00, PME_IO_BASE_ADDR + 0x56); /* FAN1 */
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outl(0x00, PME_IO_BASE_ADDR + 0x57); /* FAN2 */
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outl(0x50, PME_IO_BASE_ADDR + 0x58); /* Fan Control */
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outl(0xff, PME_IO_BASE_ADDR + 0x59); /* Fan1 Tachometer */
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outl(0xff, PME_IO_BASE_ADDR + 0x5a); /* Fan2 Tachometer */
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outl(0x00, PME_IO_BASE_ADDR + 0x5b); /* Fan1 Preload */
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outl(0x00, PME_IO_BASE_ADDR + 0x5c); /* Fan2 Preload */
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outl(0x00, PME_IO_BASE_ADDR + 0x5d); /* LED1 */
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outl(0x00, PME_IO_BASE_ADDR + 0x5e); /* LED2 */
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outl(0x00, PME_IO_BASE_ADDR + 0x5f); /* Keyboard Scan Code */
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outb(0xaa, port); /* Exit the configuration state. */
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define PME_DEV PNP_DEV(0x2e, 0x0a)
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#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
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#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
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/* Early mainboard specific GPIO setup. */
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static void mb_gpio_init(void)
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{
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device_t dev;
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uint16_t port;
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uint32_t set_gpio;
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/* Southbridge GPIOs. */
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/* Set the LPC device statically. */
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dev = PCI_DEV(0x0, 0x1f, 0x0);
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/* Set the value for GPIO base address register and enable GPIO. */
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pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
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pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
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/* Set GPIO23 to high, this enables the LAN controller. */
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udelay(10);
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set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
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set_gpio |= 1 << 23;
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outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
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/* Super I/O GPIOs. */
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dev = PME_DEV;
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port = dev >> 8;
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/* Enter the configuration state. */
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outb(0x55, port);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
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pnp_set_enable(dev, 1);
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/* GP21 - LED_RED */
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outl(0x01, PME_IO_BASE_ADDR + 0x2c);
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/* GP30 - FAN2_TACH */
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outl(0x05, PME_IO_BASE_ADDR + 0x33);
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/* GP31 - FAN1_TACH */
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outl(0x05, PME_IO_BASE_ADDR + 0x34);
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/* GP32 - FAN2_CTRL */
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outl(0x04, PME_IO_BASE_ADDR + 0x35);
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/* GP33 - FAN1_CTRL */
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outl(0x04, PME_IO_BASE_ADDR + 0x36);
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/* GP34 - AUD_MUTE_OUT_R */
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outl(0x00, PME_IO_BASE_ADDR + 0x37);
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/* GP36 - KBRST */
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outl(0x00, PME_IO_BASE_ADDR + 0x39);
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/* GP37 - A20GATE */
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outl(0x00, PME_IO_BASE_ADDR + 0x3a);
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/* GP42 - GPIO_PME_OUT */
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outl(0x00, PME_IO_BASE_ADDR + 0x3d);
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/* GP50 - SER2_RI */
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outl(0x05, PME_IO_BASE_ADDR + 0x3f);
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/* GP51 - SER2_DCD */
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outl(0x05, PME_IO_BASE_ADDR + 0x40);
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/* GP52 - SER2_RX */
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outl(0x05, PME_IO_BASE_ADDR + 0x41);
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/* GP53 - SER2_TX */
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outl(0x04, PME_IO_BASE_ADDR + 0x42);
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/* GP55 - SER2_RTS */
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outl(0x04, PME_IO_BASE_ADDR + 0x44);
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/* GP56 - SER2_CTS */
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outl(0x05, PME_IO_BASE_ADDR + 0x45);
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/* GP57 - SER2_DTR */
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outl(0x04, PME_IO_BASE_ADDR + 0x46);
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/* GP60 - LED_GREEN */
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outl(0x01, PME_IO_BASE_ADDR + 0x47);
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/* GP61 - LED_YELLOW */
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outl(0x01, PME_IO_BASE_ADDR + 0x48);
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/* GP3 */
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outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
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/* GP4 */
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outl(0x04, PME_IO_BASE_ADDR + 0x4e);
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/* FAN1 */
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outl(0x01, PME_IO_BASE_ADDR + 0x56);
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/* FAN2 */
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outl(0x01, PME_IO_BASE_ADDR + 0x57);
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/* Fan Control */
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outl(0x50, PME_IO_BASE_ADDR + 0x58);
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/* Fan1 Tachometer */
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outl(0xff, PME_IO_BASE_ADDR + 0x59);
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/* Fan2 Tachometer */
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outl(0xff, PME_IO_BASE_ADDR + 0x5a);
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/* LED1 */
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outl(0x00, PME_IO_BASE_ADDR + 0x5d);
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/* LED2 */
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outl(0x00, PME_IO_BASE_ADDR + 0x5e);
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/* Keyboard Scan Code */
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outl(0x00, PME_IO_BASE_ADDR + 0x5f);
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/* Exit the configuration state. */
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outb(0xaa, port);
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}
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@ -1,120 +1,143 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
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*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define PME_DEV PNP_DEV(0x2e, 0x0a)
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#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
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#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
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/* Early mainboard specific GPIO setup. */
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static void mb_gpio_init(void)
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{
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device_t dev;
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uint16_t port;
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uint32_t set_gpio;
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/* Southbridge GPIOs. */
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/* Set the LPC device statically. */
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dev = PCI_DEV(0x0, 0x1f, 0x0);
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/* Set the value for GPIO base address register and enable GPIO. */
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pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
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pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
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/* Set GPIO25 to input and drive GPIO23 to high,
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* this enables the LAN controller.
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*/
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udelay(10);
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set_gpio = 0x0000ffff;
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set_gpio |= 1 << 25;
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outl(set_gpio, ICH_IO_BASE_ADDR + 0x04);
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set_gpio = 0x1b3f0000;
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set_gpio |= 1 << 23;
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outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
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/* Super I/O GPIOs. */
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dev = PME_DEV;
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port = dev >> 8;
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outb(0x55, port); /* Enter the configuration state. */
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
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pnp_set_enable(dev, 1);
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outl(0x03, PME_IO_BASE_ADDR + 0x1e); /* Force Disk Change */
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outl(0x02, PME_IO_BASE_ADDR + 0x1f); /* Floppy Data Rate */
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outl(0x81, PME_IO_BASE_ADDR + 0x20); /* UART1 FIFO */
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outl(0x81, PME_IO_BASE_ADDR + 0x21); /* UART2 FIFO */
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outl(0x00, PME_IO_BASE_ADDR + 0x22); /* Device Disable */
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outl(0x01, PME_IO_BASE_ADDR + 0x23); /* GP10 */
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outl(0x01, PME_IO_BASE_ADDR + 0x24); /* GP11 */
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outl(0x01, PME_IO_BASE_ADDR + 0x25); /* GP12 */
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outl(0x01, PME_IO_BASE_ADDR + 0x26); /* GP13 */
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outl(0x01, PME_IO_BASE_ADDR + 0x27); /* GP14 */
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outl(0x01, PME_IO_BASE_ADDR + 0x28); /* GP15 */
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outl(0x01, PME_IO_BASE_ADDR + 0x29); /* GP16 */
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outl(0x01, PME_IO_BASE_ADDR + 0x2a); /* GP17 */
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outl(0x01, PME_IO_BASE_ADDR + 0x2b); /* GP20 */
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outl(0x01, PME_IO_BASE_ADDR + 0x2c); /* GP21 */
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outl(0x01, PME_IO_BASE_ADDR + 0x2d); /* GP22 */
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outl(0x01, PME_IO_BASE_ADDR + 0x2f); /* GP24 */
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outl(0x01, PME_IO_BASE_ADDR + 0x30); /* GP25 */
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outl(0x01, PME_IO_BASE_ADDR + 0x31); /* GP26 */
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outl(0x01, PME_IO_BASE_ADDR + 0x32); /* GP27 */
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outl(0x05, PME_IO_BASE_ADDR + 0x33); /* GP30 */
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outl(0x05, PME_IO_BASE_ADDR + 0x34); /* GP31 */
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outl(0x84, PME_IO_BASE_ADDR + 0x35); /* GP32 */
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outl(0x84, PME_IO_BASE_ADDR + 0x36); /* GP33 */
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outl(0x00, PME_IO_BASE_ADDR + 0x37); /* GP34 */
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outl(0x04, PME_IO_BASE_ADDR + 0x38); /* GP35 */
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outl(0x01, PME_IO_BASE_ADDR + 0x39); /* GP36 */
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outl(0x01, PME_IO_BASE_ADDR + 0x3a); /* GP37 */
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outl(0x01, PME_IO_BASE_ADDR + 0x3b); /* GP40 */
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outl(0x01, PME_IO_BASE_ADDR + 0x3c); /* GP41 */
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outl(0x86, PME_IO_BASE_ADDR + 0x3d); /* GP42 */
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outl(0x01, PME_IO_BASE_ADDR + 0x3e); /* GP43 */
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outl(0x05, PME_IO_BASE_ADDR + 0x3f); /* GP50 */
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outl(0x05, PME_IO_BASE_ADDR + 0x40); /* GP51 */
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||||
outl(0x05, PME_IO_BASE_ADDR + 0x41); /* GP52 */
|
||||
outl(0x04, PME_IO_BASE_ADDR + 0x42); /* GP53 */
|
||||
outl(0x05, PME_IO_BASE_ADDR + 0x43); /* GP54 */
|
||||
outl(0x04, PME_IO_BASE_ADDR + 0x44); /* GP55 */
|
||||
outl(0x05, PME_IO_BASE_ADDR + 0x45); /* GP56 */
|
||||
outl(0x04, PME_IO_BASE_ADDR + 0x46); /* GP57 */
|
||||
outl(0x01, PME_IO_BASE_ADDR + 0x47); /* GP58 */
|
||||
outl(0x01, PME_IO_BASE_ADDR + 0x48); /* GP59 */
|
||||
outl(0x00, PME_IO_BASE_ADDR + 0x4b); /* GP1 */
|
||||
outl(0x04, PME_IO_BASE_ADDR + 0x4c); /* GP2 */
|
||||
outl(0xc0, PME_IO_BASE_ADDR + 0x4d); /* GP3 */
|
||||
outl(0x00, PME_IO_BASE_ADDR + 0x4e); /* GP4 */
|
||||
outl(0x04, PME_IO_BASE_ADDR + 0x4f); /* GP5 */
|
||||
outl(0x00, PME_IO_BASE_ADDR + 0x50); /* GP6 */
|
||||
outl(0x01, PME_IO_BASE_ADDR + 0x56); /* FAN1 */
|
||||
outl(0x01, PME_IO_BASE_ADDR + 0x57); /* FAN2 */
|
||||
outl(0x58, PME_IO_BASE_ADDR + 0x58); /* Fan Control */
|
||||
outl(0xff, PME_IO_BASE_ADDR + 0x59); /* Fan1 Tachometer */
|
||||
outl(0x50, PME_IO_BASE_ADDR + 0x5a); /* Fan2 Tachometer */
|
||||
outl(0x00, PME_IO_BASE_ADDR + 0x5b); /* Fan1 Preload */
|
||||
outl(0x00, PME_IO_BASE_ADDR + 0x5c); /* Fan2 Preload */
|
||||
outl(0x00, PME_IO_BASE_ADDR + 0x5d); /* LED1 */
|
||||
outl(0x00, PME_IO_BASE_ADDR + 0x5e); /* LED2 */
|
||||
outl(0x00, PME_IO_BASE_ADDR + 0x5f); /* Keyboard Scan Code */
|
||||
outb(0xaa, port); /* Exit the configuration state. */
|
||||
}
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define PME_DEV PNP_DEV(0x2e, 0x0a)
|
||||
#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
|
||||
#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
|
||||
|
||||
/* Early mainboard specific GPIO setup. */
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
device_t dev;
|
||||
uint16_t port;
|
||||
uint32_t set_gpio;
|
||||
|
||||
/* Southbridge GPIOs. */
|
||||
/* Set the LPC device statically. */
|
||||
dev = PCI_DEV(0x0, 0x1f, 0x0);
|
||||
|
||||
/* Set the value for GPIO base address register and enable GPIO. */
|
||||
pci_write_config32(dev, GPIO_BASE_ICH0_5, (ICH_IO_BASE_ADDR | 1));
|
||||
pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10);
|
||||
|
||||
/* Set GPIO23 to high, this enables the LAN controller. */
|
||||
udelay(10);
|
||||
set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
|
||||
set_gpio |= 1 << 23;
|
||||
outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
|
||||
|
||||
/* Super I/O GPIOs. */
|
||||
dev = PME_DEV;
|
||||
port = dev >> 8;
|
||||
|
||||
/* Enter the configuration state. */
|
||||
outb(0x55, port);
|
||||
pnp_set_logical_device(dev);
|
||||
pnp_set_enable(dev, 0);
|
||||
pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
|
||||
pnp_set_enable(dev, 1);
|
||||
|
||||
/* GP21 - LED_RED */
|
||||
outl(0x01, PME_IO_BASE_ADDR + 0x2c);
|
||||
|
||||
/* GP30 - FAN2_TACH */
|
||||
outl(0x05, PME_IO_BASE_ADDR + 0x33);
|
||||
|
||||
/* GP31 - FAN1_TACH */
|
||||
outl(0x05, PME_IO_BASE_ADDR + 0x34);
|
||||
|
||||
/* GP32 - FAN2_CTRL */
|
||||
outl(0x04, PME_IO_BASE_ADDR + 0x35);
|
||||
|
||||
/* GP33 - FAN1_CTRL */
|
||||
outl(0x04, PME_IO_BASE_ADDR + 0x36);
|
||||
|
||||
/* GP34 - AUD_MUTE_OUT_R */
|
||||
outl(0x00, PME_IO_BASE_ADDR + 0x37);
|
||||
|
||||
/* GP36 - KBRST */
|
||||
outl(0x00, PME_IO_BASE_ADDR + 0x39);
|
||||
|
||||
/* GP37 - A20GATE */
|
||||
outl(0x00, PME_IO_BASE_ADDR + 0x3a);
|
||||
|
||||
/* GP42 - GPIO_PME_OUT */
|
||||
outl(0x00, PME_IO_BASE_ADDR + 0x3d);
|
||||
|
||||
/* GP50 - SER2_RI */
|
||||
outl(0x05, PME_IO_BASE_ADDR + 0x3f);
|
||||
|
||||
/* GP51 - SER2_DCD */
|
||||
outl(0x05, PME_IO_BASE_ADDR + 0x40);
|
||||
|
||||
/* GP52 - SER2_RX */
|
||||
outl(0x05, PME_IO_BASE_ADDR + 0x41);
|
||||
|
||||
/* GP53 - SER2_TX */
|
||||
outl(0x04, PME_IO_BASE_ADDR + 0x42);
|
||||
|
||||
/* GP55 - SER2_RTS */
|
||||
outl(0x04, PME_IO_BASE_ADDR + 0x44);
|
||||
|
||||
/* GP56 - SER2_CTS */
|
||||
outl(0x05, PME_IO_BASE_ADDR + 0x45);
|
||||
|
||||
/* GP57 - SER2_DTR */
|
||||
outl(0x04, PME_IO_BASE_ADDR + 0x46);
|
||||
|
||||
/* GP60 - LED_GREEN */
|
||||
outl(0x01, PME_IO_BASE_ADDR + 0x47);
|
||||
|
||||
/* GP61 - LED_YELLOW */
|
||||
outl(0x01, PME_IO_BASE_ADDR + 0x48);
|
||||
|
||||
/* GP3 */
|
||||
outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
|
||||
|
||||
/* GP4 */
|
||||
outl(0x04, PME_IO_BASE_ADDR + 0x4e);
|
||||
|
||||
/* FAN1 */
|
||||
outl(0x01, PME_IO_BASE_ADDR + 0x56);
|
||||
|
||||
/* FAN2 */
|
||||
outl(0x01, PME_IO_BASE_ADDR + 0x57);
|
||||
|
||||
/* Fan Control */
|
||||
outl(0x50, PME_IO_BASE_ADDR + 0x58);
|
||||
|
||||
/* Fan1 Tachometer */
|
||||
outl(0xff, PME_IO_BASE_ADDR + 0x59);
|
||||
|
||||
/* Fan2 Tachometer */
|
||||
outl(0xff, PME_IO_BASE_ADDR + 0x5a);
|
||||
|
||||
/* LED1 */
|
||||
outl(0x00, PME_IO_BASE_ADDR + 0x5d);
|
||||
|
||||
/* LED2 */
|
||||
outl(0x00, PME_IO_BASE_ADDR + 0x5e);
|
||||
|
||||
/* Keyboard Scan Code */
|
||||
outl(0x00, PME_IO_BASE_ADDR + 0x5f);
|
||||
|
||||
/* Exit the configuration state. */
|
||||
outb(0xaa, port);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue