Commit Graph

1511 Commits

Author SHA1 Message Date
Patrick Georgi 407a279461 libpayload: Align main() data types
One of many steps to compile with -Wconversion, as unsigned int and int
aren't the same thing.

BUG=b:111443775
BRANCH=none
TEST=make junit.xml shows fewer warnings with -Wconversion enabled

Change-Id: I9673ca70da32a1e5117b27fa89167e03379af9c1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-05 22:37:19 +00:00
Julius Werner d371cf3336 Make common macros double-evaluation safe
I just got hit by a double-evaluation bug again, it's time to attempt
to fix this once more. Unfortunately there are several issues that don't
make this easy:

 - bitfield variables don't support typeof()
 - local macro variables that shadow others trigger -Werror=shadow
 - sign warnings with integer literal and unsigned var in typeof-MIN()
 - ({ statement expressions }) can not be used outside functions
 - romcc doesn't support any of the fancy GCC/clang extensions

This patch tries to address all of them as far as possible with macro
magic. We don't have the technology to solve the bitfield and
non-function context issues yet (__builtin_choose_expr() still throws a
"no statement expression outside a function" error if it's only in the
branch that's not chosen, unfortunately), so we'll have to provide
alternative macros for use in those cases (and we'll avoid making
__ALIGN_MASK() double-evaluation safe for now, since it would be
annoying to do that there and having an alignment mask with side
effects seems very unlikely). romcc can continue using unsafe versions
since we're hopefully not writing a lot of new code for it. Sign
warnings can be avoided in literal/variable comparisons by always using
the type of the variable there. Shadowing is avoided by picking very
explicit local variable names and using a special __COUNTER__ solution
for MIN() and MAX() (the only ones of these you're likely to nest).

Also add DIV_ROUND_UP() to libpayload since it's a generally quite
useful thing to have.

Change-Id: Iea35156c9aa9f6f2c7b8f00991418b746f44315d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-04 19:38:31 +00:00
Matt DeVillier 74dec7f51d payloads/tianocore: Don't fail on resetting boot logo
If using a commit/branch which doesn't use a boot logo,
we don't want the build to fail unnecessarily

Test: build with upstream Tianocore commit hash,
avoid failure after successful compilation.

Change-Id: Ic41bacbb97926e9538f434aecc0f0eebc5f6326f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-02 16:32:48 +00:00
Jacob Garber b6d91753fc payloads/coreinfo: Free buffer before returning
This fixes a memory leak, which was partially resolved in
2d1e0eb (payloads/coreinfo: Free buffer before returning).

Found-by: Coverity Scan, CID 1373370 (RESOURCE_LEAK)
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I0efe94b9dfb27746828055427029c01c7f407ec2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32094
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-01 08:02:38 +00:00
Xiang Wang 9d4a169532 payload: Only display `FIT support` on ARM64 platforms
Change-Id: Ided1cc22173342fa751b84db5f08a5cf7408941d
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-28 06:38:02 +00:00
Julius Werner 78134b0ccd libpayload: strtoull: Fix edge case bug with *endptr
strtoull() can optionally take a second pointer as an out-parameter that
will be adjusted to point to the end of the parsed string. This works
almost right, but misses two important edge cases: firstly,when the
parsed string is "0", the function will interpret the leading '0' as an
octal prefix, so that the first actually parsed digit is already the
terminating '\0' byte. This will cause the function to early abort,
which still (correctly) returns 0 but doesn't adjust *endptr.

The early abort is pointless anyway -- the only other thing the function
does is run a for-loop whose condition is the exact inverse (so it's
guaranteed to run zero iterations in this case) and then adjust *endptr
(which we want). So just take it out. This also technically corrects the
behavior of *endptr for a completely invalid string, since the strtoull
man page says

> If there were no digits at all, strtoul() stores the original value of
> nptr in *endptr (and returns 0).

The second issue occurs when the parsed string is "0x" without another
valid digit behind it. In this case, we will still jump over the 0x
prefix so that *endptr is set to the first byte after that. The correct
interpretation in this case is that there is no 0x prefix, and instead a
valid 0 digit with the 'x' being invalid garbage at the end. By not
skipping the prefix unless there's at least one valid digit after it, we
get the correct behavior of *endptr pointing to the 'x'.

Change-Id: Idddd74e18e410a9d0b6dce9512ca0412b9e2333c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-26 11:25:41 +00:00
Paul Menzel fb83ff1a8b payloads/seabios: Update stable from 1.12.0 to 1.12.1
The two commits below were supplied to the stable branch.

1.  7d63249 tpm: Check for TPM related ACPI tables before attempting hw
    probe

2.  a5cab58 (tag: rel-1.12.1, origin/1.12-stable) usb-ehci: Clear pipe
    token on pipe reallocate

Change-Id: I7f1165d87950145e0538eac094c5bb9bfca4db3c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-21 12:17:17 +00:00
Joel Kitching 8d0f59935d vboot: make vboot workbuf available to payload
Create a new cbtable entry called VBOOT_WORKBUF for
storing a pointer to the vboot workbuf within the
vboot_working_data structure.

BUG=b:124141368, b:124192753
TEST=Build and deploy to eve
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
BRANCH=none

Change-Id: Id68f43c282939d9e1b419e927a14fe8baa290d91
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31887
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-19 21:43:02 +00:00
Nitheesh Sekar ef75cca0e1 libpayload: qcs405: Add new Configs
Add Additional configs to enable Timer and CHROMEOS build.

TEST=build

Change-Id: I15273fdacab0a23e05e821c433cf939be35fab97
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18 18:18:42 +00:00
Julius Werner eab2a29c8b payloads: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of

 find payloads/ -type f | \
   xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I883b03b189f59b5d998a09a2596b0391a2d5cf33
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-07 17:15:30 +00:00
Julius Werner 496ef1a9e9 Add new CONFIG(XXX) macro to replace IS_ENABLED(CONFIG_XXX)
The IS_ENABLED() macro is pretty long and unwieldy for something so
widely used, and often forces line breaks just for checking two Kconfigs
in a row. Let's replace it with something that takes up less space to
make our code more readable. From now on,

 if (IS_ENABLED(CONFIG_XXX))
 #if IS_ENABLED(CONFIG_XXX)

shall become

 if (CONFIG(XXX))
 #if CONFIG(XXX)

Change-Id: I2468427b569b974303084574125a9e1d9f6db596
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-07 17:06:28 +00:00
Matt DeVillier ee69f73dbf payloads/tianocore: remove single branch checkout parameter
using '--single-branch' when cloning the tianocore repo
prevents the use of other branches/commits outside of the
checked-out coreboot_fb branch, so remove it.

Test: build with TIANOCORE_REVISION selected and revision
set to origin/master, verify checkout succeeds

Change-Id: If8c93aa87957ba2ff9ab7a58e84d2a25b48ec346
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-04 13:56:08 +00:00
Hung-Te Lin 4708612061 fmap: Add FMAP_AREA_PRESERVE
When updating firmware, we may need to preserve some sections like VPD,
calibration data, ... etc. The logic can be hard-coded in updater as a
list of known names, but a better solution is to have that directly
declared inside FMAP area flags.

To do that, the first step is to apply the changes in flash map
(http://crosreview.com/1493767). A new FMAP_AREA_PRESERVE is now
defined and will be set in future with new syntax in FMD parser.

BUG=chromium:936768
TEST=make; boots an x86 image.

Change-Id: Idba5c8d4a4c5d272f22be85d2054c6c0ce020b1b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-04 13:25:01 +00:00
Duncan Laurie 3b29acaffa libpayload: i8042: Only test PS/2 AUX port when enabled
If a PS/2 AUX device is not present then the AUX test command
during i8042_probe() will time out and add ~500ms to the boot time.

In order to avoid this only test the PS/2 AUX port if
CONFIG_LP_PC_MOUSE is enabled.

BUG=b:126633269
TEST=boot on device without AUX port and check that this command
does not get executed, saving ~500ms at boot.

Change-Id: I2ebdecc66933bd33d320b17aa4608caf4aaf54aa
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-02 06:17:49 +00:00
Duncan Laurie 5aa0e925bc libpayload: keyboard: Add option to ignore failures during init
If keys are pressed at boot some keyboard controllers will not
properly respond with an ACK to commands, which results in the
keyboard_init function aborting before it adds the keyboard to the
input device list.

This same keyboard controller will manage to properly return keyboard
data when keys are pressed later, so it is possible for it to be
functional in the payload even if it does not respond properly to
every command during initialization.

In order to allow payloads to use the keyboard when this happens a
new Kconfig option is added to ignore the keyboard ACK response and
always add the keyboard to the input device list.  This option is
disabled by default and must be enabled by the specific boards that
need it.

BUG=b:126633269
TEST=boot on device with this controller and press keys during boot
and see that the keyboard is still functional in the payload.

Change-Id: Icc6053f99804f1b57d785cb04235b5c4b8d5426f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-02 06:17:36 +00:00
Matt DeVillier ff79341a80 payloads/tianocore: Add option for custom bootsplash
Add Kconfig options to use custom bootsplash file,
dependent on using MrChromebox's stable branch, with
help info conveying required file format.

Adjust Makefile to copy the custom bootsplash and
overwrite the default Logo.bmp file, handling both
absolute and relative paths, and restore the original
logo file after building so as to keep the working
directory clean.

Test: build with and without custom bootsplash, ensure
correct bootsplash displayed

Change-Id: I164f46777169801cff56633fd920bc81b7c8129a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-01 10:06:02 +00:00
You-Cheng Syu c60c3269ec libpayload: cbfs: Check decompressed size when loading files
After loading compressed files in CBFS, we should check the decompressed
size is equal to the expected size. This might help us detect file
content corruption or compressor/decompressor bugs.

BUG=none
BRANCH=none
TEST=manually (we can still boot into kernel on Kukui, and verify that
     loading files from CBFS still works by seeing ChromiumOS firmware
     screen).

Change-Id: Ia756cc5477670dd0d1d8aa59d4160ab4233c6795
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/31564
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28 13:56:45 +00:00
You-Cheng Syu 5ec1d24974 libpayload: cbfs: Require input size and output size for cbfs_decompress
Currently, cbfs_decompress() calls ulzma() and ulz4f() for LZMA/LZ4
decompression. These two functions don't accept input/output size as
parameters. We can make cbfs_decompress more robust by calling ulzman()
and ulz4fn() instead. This could prevent us from overflowing destination
buffer.

BUG=none
BRANCH=none
TEST=boot into kernel on Kukui with COMPRESSED_PAYLOAD_LZMA /
     COMPRESSED_PAYLOAD_LZ4.

Change-Id: Ibe617825bd000ed618791d8e3c5f65bbbd5f7e33
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/31606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2019-02-28 13:56:26 +00:00
Matt DeVillier 38b6ccfed9 payloads/tianocore: default to MrChromebox's working branch
Rather than attempt to maintain patches against upstream Tianocore, use
MrChromebox's coreboot framebuffer branch as the default build target.

Rework the Makefile to default to MrChromebox's coreboot_fb branch, but
also allow for aribitrary commits from upstream Tianocore to be used
as build targets.

Ensure the branch is synced on each build, as long as working directory
is clean, and that switching between commits or trees is handled sanely.

Eliminate TIANOCORE_MASTER as a selectable build target, since unpatched
it is unlikely to boot on any device. It can easily be specified via
the 'revision' option if desired.

Test: build for the default stable target, for upstream/master
as the specified revision, and for an arbitrary valid commit hash.

Change-Id: I4a83db3cd64c7d5b652c6e95780d10051f143e88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-26 11:13:11 +00:00
Nico Huber 1653cc7079 libpayload/sys/types.h: Add definition for off_t
`off_t` is supposed to be signed, but has no (minimum) width
specified. We'll assume 32-bit minimum, like a `signed long int`.

Also include `sys/types.h` in `libpayload.h` so everything is
available through the latter.

Change-Id: I6c0c1bc1a959db7863cbad2ba29318da162431be
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-13 12:03:03 +00:00
Philipp Hug b2566f207e libpayload: add memchr to libc
libfdt requires memchr. Add missing function to libc.

Change-Id: I872026559d16a352f350147c9d7c4be97456a99f
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/31354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-11 23:17:37 +00:00
Nico Huber 845a96dfd6 Kconfig: Remove symbol names for choices
These are completely throwing Kconfig off, resulting in duplicate
entries.

Change-Id: I401467da686d5011a456b661a10170492a919c81
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24 13:41:31 +00:00
Jonathan Neuschäfer 45e6c82e68 Fix typos involving "the the"
Change-Id: I179264ee6681a7ba4488b9f1c6bce1a19b4e1772
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-18 13:24:28 +00:00
Martin Roth 3a2aa45eeb libpayload: Don't try to use invalid row count
console->scroll_up() was hanging when console->rows is 0.  This
was happening on delan if no screen was attached.  If there are no
rows, just return.

BUG=b:119234919
TEST=Boot delan with no flat panel.  System boots to OS

Change-Id: Ib022d3c6fc0c9cf360809dca28761a50c787304a
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-12-09 09:30:13 +00:00
Julius Werner 378ec8b0de libpayload: Remove unused timer/serial drivers
This patch removes several timer and serial drivers (and configs) that
were specific to platforms which have been dropped in coreboot.

Change-Id: I589ca7f1a3b479f1c2b1b668a175a71583441ac9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2018-12-05 14:07:17 +00:00
Marcello Sylvester Bauer f1d6883a99 LinuxBoot: fix initramfs xz compression
Add the flag '--check=crc32' to the xz compression to use CRC32 for the
integrity check. The linux kernel does not support CRC64 for integrity
checks, which is the default flag on most xz applications.

Change-Id: I738bd99ef22aa053dc198df5595e1878069de13e
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/c/29935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-30 10:24:40 +00:00
Marcello Sylvester Bauer e102c5d54b LinuxBoot: refactor u-root.mk
Clean the u-root initramfs integration and add essential flags as options.
Now u-root automatically fetch updates and rebuilts itself to apply changes.

Change-Id: Id978ed2ebeff96c5be4f74ae07df9be76e106a1b
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/c/29778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-28 18:32:41 +00:00
Marcello Sylvester Bauer 78d0256f1d LinuxBoot: refactor payload
Clean and refactor the structure of the LinuxBoot payload integration,
to make it more modular and readable. The kernel and initramfs should
handled in separated makefiles.

tested with:
- qemu-i440fx (x86, x86_64)
- cavium CN8100 (arm64)

Change-Id: I41d0275a5f7efb920e881f43b0acda29f41ee221
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/c/29581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-28 18:28:45 +00:00
Marcello Sylvester Bauer 5d8f02f3ef payloads/external/SeaBIOS/Kconfig: relax native VGA dependency
Allow the inclusion of a generated option rom despite the presence of a
VGA BIOS. It is useful for dual graphics with an Intel GPU.

Change-Id: Ic3a219c2dc2133c3328192840538f0fbd1ed935a
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/c/29823
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-28 18:28:15 +00:00
Elyes HAOUAS 1e008e0e0e payloads/libpayload/libcbfs: Remove duplicated ';' at end of line
Change-Id: Id3750e839fc277e22387b78e938cc59bb3902697
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29846
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-28 11:54:21 +00:00
Martin Kepplinger 9c71596493 payloads/seabios: Update stable from 1.11.2 to 1.12.0
SeaBIOS 1.12.0 has been tagged. News are

* Initial support for "TPM CRB" hardware
* Improved cdrom media reporting in the boot menu on QEMU
* Improved floppy support on real floppy hardware
* SeaVGABIOS support for QEMU "bochs-display" and QEMU "ramfb" displays
* Several bug fixes and code cleanups

among others, see http://seabios.org/Releases

Tested by running it on a Thinkpad X230.

Change-Id: I5f8364977ce957d3e8d84d7b046d1cec36b8da6a
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/c/29724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-22 14:50:25 +00:00
Piotr Król ef676b143e payloads/tianocore: rebase patches to UDK2018 release
Patches should be applied against edk2 release instead of arbitrary
commit. This aims to simplify Tianocore payload support by other
platforms.

Change-Id: Ib409f6f93eb64d7a9a2f09a75f8e637ab8689410
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/27615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-21 15:51:07 +00:00
Marcello Sylvester Bauer a4266691e3 Linux/Linuxboot: share cmdline and initrd parser
Merge the command-line and initramfs parser from 'a linux payload'
and 'LinuxBoot'.

GOAL: merge 'a Linux payload' and 'LinuxBoot'

Change-Id: I2d2aef5d07453b98e115af6ee06318c690def785
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29510
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16 10:01:20 +00:00
Richard Spiegel 509d99ca6b payloads/libpayload/drivers/storage: Get rid of void pointer math
Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. In this particular
situation, dev->buf is already pointer to u8, and there's no need to convert
to void *.

BUG=b:118484178
TEST=Build libpayload.

Change-Id: Ib70b8ce11abc88c35be4092f097cfff385921f46
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16 09:42:34 +00:00
Richard Spiegel b93796d624 payloads/coreinfo/cbfs_module.c: Get rid of void pointer math
Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. Change the pointers
or add parenthesis to force a proper order that will not cause compile
errors if compiled with a different compiler, and more importantly, don't
have unsuspected side effects.

BUG=b:118484178
TEST=Build coreinfo with original code, run objdump and saved output. Added
modifications, build coreinfo again, run objdump again, compared objdump
outputs.

Change-Id: I1bbdc9499d257c5051fd7a86ca8b5c68bbf2e81d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29344
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-06 01:46:47 +00:00
Marcello Sylvester Bauer 9d3b1b206c Linuxboot: remove initramfs path entry
Remove Linuxboot initramfs path entry in Kconfig.
Custom initramfs can and should be used with 'Linux payload'.

Change-Id: I648fb2e0383d20b0e4d50e416af637ea07d1efb4
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-05 20:57:38 +00:00
Marcello Sylvester Bauer 28e0cb4b23 Linuxboot: check go version
Check if the installed Golang version is >= 1.9.

Change-Id: I9fd74fa8dc5e906e8b54ff5afaf69609fe957960
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29445
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-05 20:56:50 +00:00
Marcello Sylvester Bauer 51f2f2eba1 LinuxBoot: use curl
Download the linux kernel tarball with curl.
Curl is already a dependency for coreboot.

Change-Id: I2e0bee3286593bd8e93b4d645242898eb9a14015
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-11-02 14:58:56 +00:00
Marcello Sylvester Bauer 78d29bff72 LinuxBoot/X86_64: Enable 8250 uart drivers
Enable 8250 uart drivers on default defconfig.

- makes it easier to debug. (qemu -nographic)
- Kernel size increases only by 20kB.

Change-Id: I8309ecf7afd74b3c4021effedcac47350b442173
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-02 14:58:05 +00:00
Marcello Sylvester Bauer 159656b661 LinuxBoot: fix custom defconfig override
The default ARCH defconfig should not override a custom defconfig.

Change-Id: I9de24497ef6296029c66a94124bc11a0bb4d0107
Signed-off-by: Marcello Sylvester Bauer <info@marcellobauer.com>
Reviewed-on: https://review.coreboot.org/29424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-02 14:57:50 +00:00
Patrick Rudolph fa5c69ff85 libpayload: Fill reg_base for debugging purposes
Fill reg_base with physical register base address.

Tested on Lenovo T500.

Change-Id: If42135c8e10b70d5ac9626521abd9cca3cf40053
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18600
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-23 06:24:47 +00:00
Elyes HAOUAS 0b5b44e004 libpayload/curses/PDCurses/doc/intro.txt: Remove unneeded whitespace
Change-Id: Ib5a0f193d54d1b6f2431f7b801678f2a983c7941
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28432
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18 17:17:35 +00:00
Wonkyu Kim af89f49b83 tianocore : Enable Serial Debug for UEFI payload Debug build
Change-Id: I29953250ca278d5b1977be3763359df5110f67c7
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/29004
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-15 22:51:34 +00:00
Patrick Rudolph ac4819de70 libpayload: Always set pciaddr
For debugging purposes always set the pciaddr attribute.
Tested on Lenovo T500.

Change-Id: I83a0e7f7196ed251fa0becc4e56bef3ca68f20f4
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18599
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-15 15:42:18 +00:00
Julius Werner f3aa6e9319 libpayload: arm64: Add GDB support
This patch adds remote GDB support for the arm64 architecture.

Change-Id: I2fa4dbca6c39f822f489a5e81bd052f53fda98a5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-12 20:17:48 +00:00
Julius Werner 1bfda7293a libpayload: gdb: Factor out gdb_handle_reentrant_exception() from arm32
The arm32 GDB architecture code contains a little hack that allows it to
(sort of) correctly deal with a reentrant exception triggered from
within the GDB stub. The main logic for this isn't really arm32 specific
and could be useful for other architectures as well, so factor it out
into a separate function.

Change-Id: I3c6db8cecf1e86bba23de6fd2ac9fdf0cf69d3c6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-12 20:17:40 +00:00
Julius Werner 5c0e72ff99 libpayload: arm64: Make exception handling closer to arm32
This patch reworks the arm64 exception handling to be more similar to
how it works on arm32. This includes a bunch of features like actually
saving and restoring more exception state in the exception_state
structure and supporting the same sort of partial reentrancy that is
useful for GDB. Since there's no instruction to directly load into or
store out of SP on arm64, we can't do quite the same thing where we use
that to read an exception_state_ptr variable right after exception entry
when no other register is available. But we can do something very
similar by (ab-)using the "high" stack pointer (SP_EL2) as a pointer to
the exception_state struct and providing a function to change it.

Change-Id: Ia16a1124be1824392a309ae1f4cb031547d184c1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-12 20:17:28 +00:00
Julius Werner ca52a25882 libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2
This patch adds the new, faster architectural register accessors to
libpayload that were already added to coreboot in CB:27881. It also
hardcodes the assumption that coreboot payloads run at EL2, which has
already been hardcoded in coreboot with CB:27880 (see rationale there).
This means we can drop all the read_current/write_current stuff which
added a lot of unnecessary helpers to check the current exception level.

This patch breaks payloads that used read_current/write_current
accessors, but it seems unlikely that many payloads deal with this stuff
anyway, and it should be a trivial fix (just replace them with the
respective _el2 versions).

Also add accessors for a couple of more registers that are required to
enable debug mode while I'm here.

Change-Id: Ic9dfa48411f3805747613f03611f8a134a51cc46
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2018-10-12 20:14:54 +00:00
Piotr Król 3c60375c57 payloads/tianocore: Fix not applying patch 06_CorebootPayloadPkg_keep_cb_table
Mentioned patch could not be applied in coreboot-sdk:1.52. With this fix
patch apply correctly.

Change-Id: I130856520f91bcfbd9a62741b1d5abb6495a6eac
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-11 01:20:06 +00:00
Philipp Hug 56dceb2e1a payloads: Only show supported payloads in menuconfig
Some payloads don't depend on their supported platforms, which makes
them visible in menuconfig even if they are not supported (yet).

Change-Id: Ia1ec0f0ca0b6521d0c024500c67326337f3d744f
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-09 11:29:52 +00:00
Patrick Rudolph eec0d9b8dc LinuxBoot/arm64: Remove firmware from defconfig
The extra firmware is not part of upstream kernel.
Fixes build error if the firmware is not present.

Change-Id: Ifbcb0bb0e2edf3aa260b40dfa339812019f9f0b3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-05 03:27:39 +00:00
Raul E Rangel 59e923d757 libpayload/x86/exception: Add ability to ignore unknown interrupts
This will make enabling the APIC safer by ignoring unknown interrupts
and not halting the system. Once all interrupt sources have been found
and handled DIE_ON_UNKNOWN_INTERRUPT can be set if desired.

BUG=b:116777191
TEST=Booted grunt, halted the kernel, and pushed the power button while
in S5. Verified that depthcharge logged the unknown exception.

APIC Init Started
APIC Configured
Ignoring interrupt vector 39

Change-Id: If4ed566ec284d69786c369f37e4e331d7f892c74
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04 15:25:17 +00:00
Raul E Rangel 44d89f526d libpayload/x86/exception.c: Remove exception_install_hook
Not used by x86 code anymore.

BUG=b:116777191
TEST=Validated that depthcharge can be built.

Change-Id: I25ad3903989a5433ce73d657cfdb93dd1f34f7b5
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04 15:24:54 +00:00
Raul E Rangel ad37763a5f libpayload/apic: Register a spurious interrupt vector
We should have a spurious interrupt vector just incase we get one. The
handler doesn't need to do anything.

BUG=b:116777191
TEST=Booted depthcharge on grunt and inspected the register. I can't
generate a spurious interrupt, so I can't validate that the handler gets
called.

Change-Id: I9e49e617f4375eb5eb00d0715c1902f77e2bf284
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04 15:24:44 +00:00
Raul E Rangel b025de0ddb libpayload/apic: Only ACK interrupts triggered by the APIC
Only set end of interrupt (EOI) when the APIC In-Service vector matches
the interrupt vector. This makes it so we don't EOI a non APIC
interrupt.

BUG=b:116777191
TEST=Booted grunt with APIC enabled and verified depthcharge still
works.

Change-Id: I00bd1e7a0fcf2fc004feadc40d22ebfefe68b384
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04 15:24:20 +00:00
Patrick Rudolph 1fea734e54 libpayload/drivers/usb: Fix leaks
Don't leak buffers on device detach.

Tested on qemu using:
qemu-system-x86_64 -bios build/coreboot.rom -M pc -m 2048 -usb \
 -device usb-ehci,id=ehci -device usb-mouse -device usb-audio,bus=usb-bus.0 \
 -device usb-bt-dongle,bus=usb-bus.0 -device usb-kbd

Change-Id: Ib2d80dd4590aa0dacdf2da3b614c6505c931d0be
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/23689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-01 16:58:29 +00:00
Patrick Rudolph d5a70bdfd5 libpayload/drivers/usb: Fix broken retry counter
Exit on first sucessful CONTROL transfer instead of doing
GET_DESCRIPTOR_TRIES iterations.

Tested on qemu using:
qemu-system-x86_64 -bios build/coreboot.rom -M pc -m 2048 -usb \
 -device usb-ehci,id=ehci -device usb-mouse -device usb-audio,bus=usb-bus.0 \
 -device usb-bt-dongle,bus=usb-bus.0 -device usb-kbd

Change-Id: I7c881c08d94636a43223338e46c876b5f3e27d47
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/23688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-01 16:54:55 +00:00
Piotr Król 80346d0490 payloads/tianocore: ignore whitespace change when applying patches
This change is required to apply patch
06_CorebootPayloadPkg_keep_cb_table since conflict in white space
between patch and target file in edk2 makes patch rejected while
building under coreboot-sdk:1.52.

Change-Id: I38f7d46925cc00a2b5c5400e3fbf3579990f3fa5
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-28 09:52:27 +00:00
Patrick Georgi 5b2a2d008f src/*: normalize Google copyright headers
As per internal discussion, there's no "ChromiumOS Authors" that's
meaningful outside the Chromium OS project, so change everything to the
contemporary "Google LLC."

While at it, also ensure consistency in the LLC variants (exactly one
trailing period).

"Google Inc" does not need to be touched, so leave them alone.

Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2018-09-28 07:13:00 +00:00
Andrea Barberio 256dd1198c payloads/Kconfig: do not show compression menu for FIT
FIT payloads do not support compression. Currently this would thrown an error
like the following:

E: FIT images don't support whole-image compression, compress the kernel component instead!

With this patch, menuconfig will correctly *not* show payload compression for
FIT payloads, and this will correctly set compression to NONE.

Change-Id: If564e2f5c0d499bc30411d7bd41611790453d4ef
Signed-off-by: Andrea Barberio <insomniac@slackware.it>
Reviewed-on: https://review.coreboot.org/28732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-26 15:38:58 +00:00
Martin Roth f2c3d8076e payloads/external: Add yabits payload
Yabits (Yet another UEFI bootloader) is designed to be a slim and quick
alternative to Tianocore.  It is still under heavy development.

https://web.archive.org/web/https://yabits.github.io/

Change-Id: I132970e952c605c73cfe33dc47f20170ae8aa899
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/28590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-16 13:10:17 +00:00
Ronald G. Minnich 95c331b94b rampayload: Add the linuxcheck payload
The i386.c file uses standard 3f8 UART for some simple diagnostic
prints, and the libpayload console otherwise.

This payload was used to debug Linux as a rampayload and was very helpful
for that work.

Change-Id: I1cce5528780cd825fd91a88137fa70abd9f218e7
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28600
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-14 09:59:17 +00:00
Lijian Zhao cf9ea55473 payloads/tianocore: Add option to use 8254 timer
Change TianoCore payload default to use HPET timer. Add an option to use
8254 timer for legacy platform support.

BUG=N/A.
TEST=Build and boot up into UEFI shell on Whiskey Lake rvp platform.

Change-Id: I857704b0ca128fc9da193ae26a33c7cf89ad7320
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2018-09-13 16:43:36 +00:00
Raul E Rangel 9fc7b8e973 libpayload/x86/delay: Make arch_ndelay call apic_delay if delay is long
This reduces power consumption on grunt by over 3W when sitting at the
depthcharge recovery screen.

BUG=b:109749762
TEST=Booted grunt in the recovery screen and made sure it continued to
work.

Change-Id: Id079c099ee4cf6a07724241af4400063f4551668
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28245
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Julius Werner <jwerner@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12 14:15:48 +00:00
Raul E Rangel 370c116ca5 libpayload/x86/delay: Add an x86 arch_ndelay
This method has a pause instruction to help the CPU relax a little bit.
Measuring grunt it saves about 80mW.

BUG=b:109749762
TEST=Made sure that grunt boots.

Change-Id: I045a941ed42fcc4f2dbdd65b5cbb42d84813f50c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28244
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12 14:15:25 +00:00
Raul E Rangel d63627fb84 libpayload/libc/time: Add an arch_ndelay()
Replace _delay with an arch_ndelay(). This way each arch can setup their
own delay mechanism.

BUG=b:109749762
TEST=Verified delay's still work on grunt.

Change-Id: I552eb30984f9c21e92dffc9d7b36873e9e2e4ac5
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28243
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-12 14:15:18 +00:00
Raul E Rangel 24ae85c3ff libpayload/x86/apic: Add an apic_delay method and calibrate the timer
The apic_delay method will halt the CPU and wait for a timer interrupt
to fire. I went with usec because nsec is too granular to guarantee.

This method will be called from an arch_ndelay() method when the delay
is large enough to justify a sleep.

BUG=b:109749762
TEST=Tested it on grunt by changing the _delay method to call
apic_delay().

Change-Id: I80363f06bdb22d0907f895885e607fde1c4c468d
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-12 14:15:11 +00:00
Raul E Rangel ac8ebd0e73 libpayload/arch/x86: Add support for initializing the APIC
This is just the bare minimum required to initialize the APIC. I only
support xAPIC and chose not to support x2APIC. We can add that
functionality later when it's required.

I also made the exception dispatcher call apic_eoi so that the callbacks
won't forget to call it.

BUG=b:109749762
TEST=Booted grunt and verified that depthcharge continued to function
and that linux booted correctly. Also verified GDB still works.

Change-Id: I420a4eadae84df088525e727b481089ef615183f
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-12 14:14:46 +00:00
Raul E Rangel f47ccbdd47 libpayload/x86/gdb: Migrate to use set_interrupt_handler
BUG=b:109749762
TEST=Verified GDB still functions by hitting Ctrl+G on the developer
screen and stepping through some code.

Change-Id: I723a8a95f681c500d9d8e35e49fd1d893cb1f133
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-10 15:01:19 +00:00
Raul E Rangel 80d5c19590 libpayload/x86/exception: Add ability to handle user defined interrupts
I need to setup the APIC timer to fire interrupts. I would like to reuse
the existing interrupt table. So I extended it to support user defined
interrupts. I just added all 255 vectors so there wouldn't need to be
any additional build time configuration.

I'm going to deprecate exception_install_hook and remove it in a follow
up. It will be replaced with set_interrupt_handler. This way the
exception lookup does not have to manage a list of callbacks, or have to
worry about the order they are processed.

BUG=b:109749762
TEST=Wrote an interrupt handler and fired an APIC timer interrupt and
verified that vector 32 was returned.

Change-Id: Id9c2583c7c3d9be4a06a25e546e64399f2b0620c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-10 15:01:04 +00:00
Martin Roth 87282737a8 payloads: Remove/fix trailing whitespace
Change-Id: Idfc54ca0ed53f52ddad61114ec6b05d94dd746c1
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-09-04 12:38:40 +00:00
Philipp Deppenwiese 9569ebeab8 payloads/LinuxBoot: Fix remaining issues
* Update kernel versions
* Fix initrd path handling

Change-Id: Ia0641fd0c0db1e47ee4829b73871af662d4a6370
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/28401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-09-04 12:36:43 +00:00
Raul E Rangel cf79c8344d libpayload/x86/exception: Add methods to enable/disable interrupts
Will be used by the APIC.

BUG=b:109749762
TEST=Verified by the other cls in the stack.

Change-Id: Id86f2719d98a90318ac625e09601e5dbb06e3765
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-23 16:24:44 +00:00
Raul E Rangel 052b5317da libpayload/x86/cpuid: Add a cpuid macro
Since libpayload doesn't link against libgcc we need to define our own
cpuid macro. I didn't add any error checking since anything in the last
decade should support cpuid.

BUG=b:109749762
TEST=called it and made sure the correct flags were returned.

Change-Id: Id09878ac80c74416d0abca83e217516a9c1afeff
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-23 16:24:38 +00:00
Stefan Tauner a07366c9f9 payloads/external/Memtest86Plus: allow for selecting a specific revision
Because the Kconfig configuration files for primary payloads are
already sourced via a wildcard pattern this change requires to
use another file name pattern.

Change-Id: I83b89f5e14618e8a487ebb044fcdd3c175662591
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-22 15:34:35 +00:00
Joel Kitching 44cff7a897 cbtable: remove chromeos_acpi from cbtable
Since we can derive chromeos_acpi's location from that of
ACPI GNVS, remove chromeos_acpi entry from cbtable and
instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET.

BUG=b:112288216
TEST=None
CQ-DEPEND=CL:1179725

Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/28190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-22 15:33:50 +00:00
Joel Kitching 75b1f768d8 cbmem: rename vdat to chromeos_acpi
There is a confusingly named section in cbmem called vdat.
This section holds a data structure called chromeos_acpi_t,
which exposes some system information to the Chrome OS
userland utility crossystem.

Within the chromeos_acpi_t structure, there is a member
called vdat.  This (currently) holds a VbSharedDataHeader.

Rename the outer vdat to chromeos_acpi to make its purpose
clear, and prevent the bizarreness of being able to access
vdat->vdat.

Additionally, disallow external references to the
chromeos_acpi data structure in gnvs.c.

BUG=b:112288216
TEST=emerge-eve coreboot, run on eve
CQ-DEPEND=CL:1164722

Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/27888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-14 14:48:44 +00:00
David Hendricks fb03dd6043 linuxboot: remove curley brace expansion from u-root commands
Curley brace expansion is a bash-ism, so we can't use it for the
u-root command list.

This unfortunately also breaks the current Kconfig option since the
list needs to be separated by space instead of commas.

Change-Id: I429a52c1673e29b7180ee6f53deaa7a551a1a9b3
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/27967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-10 09:05:04 +00:00
Raul E Rangel 8346a44dd1 libpayload/drivers/usb/xhci: Replace raw values with constants
BUG=none
TEST=compiled on grunt and made sure USB still works in depthcharge

Change-Id: I972f4604bb5ff3838cb15f323c5a579ad890ecf5
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08 21:57:22 +00:00
Piotr Król bb95731dad payloads/external/SeaBIOS: add support for sercon port
Change-Id: Id2d2ed0fa97f2cef5818a8508bb8ee3ddba73647
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/26060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-06 14:16:17 +00:00
Raul E Rangel a8b4b75d24 exception: Fix segment error code mask
The segment error descriptor is actually 13 bits long.

BUG=b:109749762
TEST=Verified by causing a segment error

Change-Id: I3439f9ce1e8cf0c472c4eb82d74a787718c9609f
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06 07:56:00 +00:00
Philipp Deppenwiese 781693f211 payload/LinuxBoot: Fix compilation and clean target
* Update kernel version
* Add kernel directory removal during clean target
* Add x86 and x86_64 default configs

Change-Id: I6793bffd2c537a0e9fe7c07abbea99b28defb52e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/27745
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-31 12:46:21 +00:00
Patrick Georgi c430ecec9e libpayload/arm64: Drop unused static array
Fixes build with gcc8.1

Change-Id: I042f79ddfb4c249e00b5b259280289b8534f6854
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/27546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-20 11:06:36 +00:00
Patrick Rudolph 02c0814764 payloads/LinuxBoot: Add ARM64 support
Add support for ARCH=ARM64 and introduce CROSS_COMPILE for all architectures.

* Always compress kernel Image using xz
* Create FIT uImage containing the kernel, initramfs and DTB
* Add ARM64 defconfig for all SoCs

Change-Id: I9a0cc248283432fb2384956ca55e687d4127398c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-19 13:54:24 +00:00
Raul E Rangel 1b43ad7149 libpayload/generic_hub: Detect port disconnect after reset
If a port disconnects after a reset we should abort any initialization
on the port. This might mean the device has re-enumerated as a 3.0 device
so the hub should be scanned again.

BUG=b:76831439
TEST=Verified USB-C devices that get detected correctly in depthcharge.

Change-Id: Iad899544684312df1bef08d69b5c7f41eac3a21c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-17 20:38:46 +00:00
Raul E Rangel d29c81d513 libpayload/xhci: Check noop return code when debugging
Make it obvious that the command has failed.

BUG=b:76831439
TEST=Verified on grunt

Change-Id: Ifa0b2fb087f5f0a36ba017a774fc98b33ab035a4
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-17 15:30:10 +00:00
Raul E Rangel c534a066d8 libpayload: Add UNKNOWN_SPEED to usb_speed enum
xhci_rh_port_speed return -1 if the port is disabled. The usb_speed enum
is unsigned so this results in a positive value which implies success.

Adding a -1 to the enum will make it signed so the >= 0 check will work
correctly.

BUG=b:76831439
TEST=verified on grunt that -1 is returned when port is disabled.

Change-Id: I98a373717d52dfb6ca4dcc53a00dc1b4c240a919
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-17 15:23:36 +00:00
Raul E Rangel 50a2a86832 libpayload: Make libpayload compile using gnu11
This matches coreboot.

BUG=b:76831439
TEST=emerge-grunt libpayload deptcharge chromeos-bootimage
then booted image

Change-Id: I3a3baa03e03a31e9e75b201ac4fa642505fc1d3a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-16 07:44:03 +00:00
Raul E Rangel 8fdc9162d9 libpayload/xhci: Document struct offsets on xhci_t
This makes it easier to know what offset each register references.

BUG=b:76831439
TEST=none

Change-Id: I92dcbd463ceb4dd8edbbd97b51a4e9aa32a983a6
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-16 07:43:50 +00:00
Paul Menzel 209a1bf8ca payloads/Kconfig: Put option *None* at the top
As *None* is special and not a payload, it makes sense to put it at the
top. Also, it was at before the latest addition of the FIT payload
choice.

Fixes: a892cde6 (lib: Add FIT payload support)
Change-Id: I52163ea9472308ecbc396012d9912b9617e0c318
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/27414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-07-10 09:53:12 +00:00
Martin Kepplinger cf243657e7 payloads/seabios: Update stable from 1.11.1 to 1.11.2
SeaBIOS 1.11.2 was tagged with the following changes:

```
f9626cc cbvga_set_mode: refine clear display logic
f88297a qemu: add qemu ramfb support
a2e4001 vgasrc: add allocate_pmm()
17b01f4 pmm: use tmp zone on oom
44b17d0 bochs_display_setup: return error on failure
4ba61fa cbvga_set_mode: disable clearmem in windows x86 emulator.
dd69189 cbvga_list_modes: don't list current mode twice
5f0e7c9 cbvga_setup_modes: use real mode number instead of 0x140
961f67c qemu: add bochs-display support
767365e cbvga: factor out cbvga_setup_modes()
7906460 optionrom: enable non-vga display devices
```

Tested by running it on a Thinkpad X230.

Change-Id: Iea13eb64b3d5af0b283bff096587a3039227b5c0
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Tested-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/27326
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-06 01:20:48 +00:00
Michał Żygowski 9839eff60a payloads/iPXE: add iPXE serial enable option
Since SeaBIOS 1.11.0 implements serial console and etc/sercon-port
runtime config file is present in CBFS, SeaBIOS additionally
redirects iPXE output to configured IO port. For boards which use
the same UART for SeaBIOS and iPXE console it causes doubled
output.

The option is enabled by default and passes UART configuration
to iPXE Makefile as before. When unselected, only SeaBIOS handles
printing output from iPXE.

Change-Id: Ia3c74cfbee4f816782161fcff286a14f46be78c5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-03 11:03:30 +00:00
Paul Menzel ab6583ece0 payloads/Kconfig: Use third-person singular in description
Change-Id: I7bbc346771cff9954839c66c8ef6f237f116241f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/27299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-03 09:22:42 +00:00
Furquan Shaikh 6756c16e82 payloads/libpayload/drivers/i8042: Disable scanning on disconnect
This change ensures that keyboard scanning is disabled and keyboard is
set to default state while disconnecting the keyboard. This is
required to ensure that the controller doesn't keep scanning and
buffering keystrokes which could lead to OS drivers reading stale
data.

BUG=b:110024487
TEST=Verified that kernel driver is able to probe correctly even if
multiple keys are pressed during handoff from payload to OS.

Change-Id: I1ffb8904d545284454c1825ee2e7c0087fc13762
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-02 07:33:38 +00:00
Furquan Shaikh 1299dc107d payloads/libpayload/drivers/i8042: Add macros for i8042 commands
This change adds macros for commands (written to 0x64) and keyboard
commands (written to 0x60) for 8042 controller.

BUG=b:110024487

Change-Id: I74b2388d048e35b5bdf5bd862d0975e88f1bd6af
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-02 07:32:33 +00:00
Patrick Rudolph 1ce225b5a3 tianocore: Add more patches
* Fix building BaseTools in hostgcc v8.1.0+
* Fix buidling tianocore on gcc v7.0.0+

Change-Id: I7e2efea930b27749b1097607ab143ce2f91e79ec
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-28 13:37:56 +00:00
T Michael Turney be073dacb0 libpayload: cheza - fix config for chromium chroot build
Add CONFIG_LP_CHROMEOS to configuration file

Change-Id: I528dee96cf5052b99b8f7573010d98fd80680688
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/26711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-22 13:11:06 +00:00
Patrick Rudolph e66b10f3e1 tianocore: Fix RPM package name
The packge uuid-devel doesn't provide the required files,
but libuuid-devel does.

Change-Id: I61d537e4f1fca0d7172c129a75e13aa58452763f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-21 17:28:55 +00:00
Nico Huber bb10ec3d41 payloads/external/GRUB2: Use pkg-config over freetype-config
`freetype-config` is gone and was obsolete for a long time.

Change-Id: Id3058e55b1630f43225d3cd1ad91801c4085874f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-21 14:57:13 +00:00
Philipp Deppenwiese 0f0e4e6c66 payloads: Add LinuxBoot payload in u-root mode
* Add LinuxBoot support
* Add u-root mode
* Download kernel and u-root from upstream sources.
* Add customization options
* Clean kernel only if directory exists

Change-Id: I3a25ff6812e046acc688cbbb203cf262ad751659
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/23071
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-19 18:37:37 +00:00
Patrick Rudolph a892cde653 lib: Add FIT payload support
* Add support for parsing and booting FIT payloads.
* Build fit loader code from depthcharge.
* Fix coding style.
* Add Kconfig option to add compiletime support for FIT.
* Add support for initrd.
* Add default compat strings
* Apply optional devicetree fixups using dt_apply_fixups

Starting at this point the CBFS payload/ can be either SELF or FIT.

Tested on Cavium SoC: Parses and loads a Linux kernel 4.16.3.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.15.0.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.1.52.

Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-19 18:10:05 +00:00
Patrick Rudolph 7ee05eddf1 util/cbfstool: Support FIT payloads
In order to support booting a GNU/Linux payload on non x86, the FIT format
should be used, as it is the defacto standard on ARM.
Due to greater complexity of FIT it is not converted to simple ELF format.

Add support for autodecting FIT payloads and add them as new CBFS_TYPE 'fit'.
The payload is included as is, with no special header.
The code can determine the type at runtime using the CBFS_TYPE field.
Support for parsing FIT payloads in coreboot is added in a follow on
commit.
Compression of FIT payloads is not supported, as the FIT sections might be
compressed itself.

Starting at this point a CBFS payload/ can be either of type FIT or SELF.

Tested on Cavium SoC.

Change-Id: Ic5fc30cd5419eb76c4eb50cca3449caea60270de
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-15 09:13:24 +00:00
Kyösti Mälkki 1dc5ce31ce coreinfo: Skip unpopulated PCI functions
Per PCI specification, function 0 must be present,
so functions 1 to 7 can be skipped in this case.

For a device that is not multi-function, it may not
decode function number in the hardware at all. To
avoid registering such a device eight times, skip
scanning functions 1 to 7.

Without the latter fix, a single-function PCI bridge
may call pci_scan_bus() second time and secondary
side devices would get appended second time in the
array devices[]. At that point, quicksort() apparently
hits an infinite recursion loop.

Since pci_scan_bus() is called in part of the early
modules->init() sequence early in main(), the errors
here left coreinfo payload completely silent when
PCI module was built-in on affected system.

Terminal screen was cleared, though.

Change-Id: Ifc6622f050b98afb7196de0cc3a863c4cdfa6c94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-14 07:59:05 +00:00
Mike Banon 794284ff0e tint: change the tint download link from HTTP Debian to HTTPS FSF
Last time there was a request to change a link from HTTP to HTTPS, also
it seems more ethical to use a link to the Free Software Foundation
server. SHA1 is the same - 7fcaa428c6d0de7096d1e4fbfd14848096ae5aad.

Change-Id: I55147ee2668de03ba6e9feb84936de24b2a001df
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/23855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-07 06:46:02 +00:00
Mike Banon 9829b6f408 tint: fix the "Paused - Press any key to continue" message for pause
Earlier this message has not been shown even at the corner of screen.
This fixes it by refreshing the screen, and moves it to the center.

Change-Id: If4e33e884c00c17f19ab330167d9293c8396ff3e
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/23854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-07 06:45:10 +00:00
Mike Banon f8b54b6315 tint: make it possible to reboot by pressing 'q' key two times
Earlier it was impossible to exit without pressing the power button.

Change-Id: Ia56d639fa8e563047fb3d2723695626a449ead40
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/23853
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07 06:44:35 +00:00
Mike Banon a16cffe480 tint: upgrade the outdated tint payload from 0.03b to 0.04+nmu1
Fixes two buffer overflows and opens a road to further improvements.
All the previous adjustments to libpayload_tint.patch (including the
latest "use the current time as random seed") have been preserved.

Change-Id: I22e65d18a0b1551f7049c4afe7f95868f584cf9b
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/23852
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07 06:41:17 +00:00
Elyes HAOUAS 012e7a4ebd libpayload/curses/{form,menu}: Fix uncountable "information"
Change-Id: I28c79d0262a54b58d353802e0d572e5b8be5fbc5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04 09:14:48 +00:00
Patrick Rudolph ae2cb2d3bf libpayload-x86: Export keyboard modifiers
Add function to get active keyboard modifiers.

Change-Id: Ifc7bd4aa86f20d67c5b542d0458b966e605c5499
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18601
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 15:31:47 +00:00
Patrick Rudolph 1f5ebf7c8b libpayload: Export usbhid_getmodifiers
Add a new method to retrieve active usb keyboard modifiers.

Change-Id: Ief6679ce782b58b9ced207f4f27504fb2a517b76
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18602
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 15:28:24 +00:00
Hannah Williams b81362a82e libpayload-x86: i8042: fix i8042_data_ready_ps2 and i8042_data_ready_aux
keyboard_disconnect was called without keyboard_init being called and in this
case keyboard_havechar returns true because i8042_data_ready_ps2 is
dereferencing uninitialized variable ps2_fifo from within fifo_is_empty causing
keyboard_disconnect to be stuck in this while loop.
while (keyboard_havechar())
    keyboard_getchar();

BUG=b:80299098
TEST=Check if the normal mode path in depthcharge is not causing a hang

Change-Id: I944b4836005c887a2715717dff2df1b5a220818e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/26590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-30 01:10:44 +00:00
Kyösti Mälkki 185202c469 libpayload: Fix payload .bss corruption
Third call to newwin() corrupted payload context.
Fix array indexing and check for boundary.

Sample payload coreinfo was affected, loader_eax
variable got corrupted on my particular build.

Change-Id: Iee98901cf57f0689f65ac43aa7e60e8aea092500
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-21 04:48:28 +00:00
Patrick Georgi e8604b8da6 libpayload: disable mouse on CHROMEOS
We already have that Kconfig flag, so I guess we should use it for
consistency.

Change-Id: I61ee6a97e369ccfe5c55d4414a5fa91c8d80ecf7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-18 16:00:18 +00:00
Ronald G. Minnich c6d134988c Revert "cbfs/payload type: Fix build warning and whitespace in name"
This reverts commit 717ba74836.

This breaks seabios and a few other payloads. This is not
ready for use.

Change-Id: I48ebe2e2628c11e935357b900d01953882cd20dd
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/26310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-16 04:50:55 +00:00
Patrick Rudolph 5afc2936b8 libpayload-x86: Add PS2 mouse driver
Make use of i8042 driver to add PS2 mouse driver support.

Tested on Lenovot T500.
The touchpad can be used to drive the mouse cursor.

Change-Id: I4be9c74467596b94d64dfa510824d8722108fe9c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-15 12:02:31 +00:00
Patrick Rudolph 52165966f3 libpayload-x86: keyboard: Use i8042 driver
Make use of i8042 driver in keyboard.c.

Required to add PS/2 mouse support.

Tested on Lenovo T500.

Change-Id: If60b5ed922b8fc4b552d0bfd9fe20c0fd6c776bf
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18596
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15 11:21:55 +00:00
Paul Menzel 717ba74836 cbfs/payload type: Fix build warning and whitespace in name
Currently, adding a payload to CBFS using the build system, the warning
below is shown.

    W: Unknown type 'payload' ignored

Update payload type from "simple elf" to "simple_elf" and rename the
word "payload" to "simple_elf" in all Makefiles.

Fixes: 4f5bed52 (cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELF)
Change-Id: Iccf6cc889b7ddd0c6ae04bda194fe5f9c00e495d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26240
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15 11:20:45 +00:00
Patrick Rudolph 9d22172558 libpayload-x86: Move keyboard.c
Move keyboard.c into i8042 folder.

Change-Id: Idd30a9082e48a451d9fe5ead3f3dda4e6396b50c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18595
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15 11:20:30 +00:00
Patrick Rudolph e6a3821b97 libpayload-x86: Add common i8042 driver
Add a common i8042 driver that uses multiple overflowing
fifos to seperate PS/2 port and PS/2 aux port.

Required to support PC keyboard and PC mouse at the same time.

Tested on Lenovo T500.

Change-Id: I4ca803bfa3ed45111776eef1f4dccd3fab02ea39
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18594
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15 11:20:06 +00:00
Patrick Rudolph 4f5bed5210 cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELF
In preparation of having FIT payloads, which aren't converted to simple ELF,
rename the CBFS type payload to actually show the format the payload is
encoded in.

Another type CBFS_TYPE_FIT will be added to have two different payload
formats. For now this is only a cosmetic change.

Change-Id: I39ee590d063b3e90f6153fe655aa50e58d45e8b0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-04 10:30:24 +00:00
Elyes HAOUAS 00877386ee payloads/libpayload: Add spaces around '=='
Change-Id: Ie1da925aceb01c2d21b472bf171000803004578f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-02 07:59:14 +00:00
T Michael Turney 9b5c28af18 libpayload: Add Timer for sdm845
Uses ARCH64 Timer

TEST=build

Change-Id: Ic312bcf3bc7e80482b7f038e2dbc4abaaffd5956
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-01 23:35:25 +00:00
T Michael Turney 1e3e02a1d2 libpayload: Add raw_read_ functions
Add: raw_read_cntfrq_el0() and raw_read_cntpct_el0()

Required to support Arch64 Timer

Change-Id: I86aa97039304b9e9336d0146febfe1811c9e075a
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-01 23:34:03 +00:00
Elyes HAOUAS 03f2536f9d libpayload/drivers/usb/ohci_private.h: Add parentheses around macro
Change-Id: Ib90564e32f5ff204aa5d856024b7eed2624a77b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-29 18:13:08 +00:00
Elyes HAOUAS 99fe7d243d libpayload/include/queue.h: Remove trailing whitespace
Change-Id: I7ff676f51958e12c40a82f56e68a776ddf429228
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-27 09:11:16 +00:00
Elyes HAOUAS 24b1305dac payloads/coreinfo/README: Remove trailing whitespace
Change-Id: I467376bab942eac1b6f1f8544bdd96202335b75d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-27 09:09:45 +00:00
Elyes HAOUAS 01afd534f4 payloads/external/tianocore: Remove trailing whitespace
Change-Id: Ibb15d370beb8ba34f24bd86eed19de38a3df3561
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-27 09:09:35 +00:00
Elyes HAOUAS 4713b5cd9e libpayload/curses/form: Remove trailing whitespace
Change-Id: I231ea26e8d8bfc53da22a440451802b425c996b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-27 09:09:17 +00:00
Elyes HAOUAS f2be550d3d payloads/libpayload/curses/menu: Remove trailing whitespace
Change-Id: Ia4bd5224a77914e0561fa35a18aec8db16bff320
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-27 09:09:07 +00:00
Duncan Laurie a96e31b469 payloads/depthcharge: Update stable version to upstream master
From commit id 61cfcc3b:
eowth: Select CONFIG_DRIVER_BUS_SPI_INTEL_GSPI_VERSION_2

To commit id 902681db:
zoombini: Enable NVMe as boot source

Change-Id: Iab7676dd642c13f58dde85940ac1c8b52bfce3b7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-26 16:35:24 +00:00
Julius Werner 39c4bb0211 libpayload: Move GDB functions to stdlib.h
When GDB support is compiled in, halt() in libpayload will call
gdb_enter(). halt() is defined in <stdlib.h> and gdb_enter() in
<libpayload.h>. Usually files just include <libpayload.h> so this is not
a problem, but in some situatons a payload may just include <stdlib.h>
(or a file including it like <assert.h>), leading to an undeclared
identifier here. Move the GDB functions to <stdlib.h> to solve this.

Change-Id: I7b23b8ac9cd302aa6ef96f24565130490ac40071
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25730
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-19 20:39:29 +00:00
Paul Menzel 0cdaad36eb Use git HTTP URLs without `/p` in it
Change-Id: I9972b138c6dd2a289880c4ec8b3fe64fc3baa66b
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/25545
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17 10:38:06 +00:00
Patrick Rudolph 57afc5e0f2 arch/arm64/armv8/mmu: Add support for 48bit VA
The VA space needs to be extended to support 48bit, as on Cavium SoCs
the MMIO starts at 1 << 47.

The following changes were done to coreboot and libpayload:
 * Use page table lvl 0
 * Increase VA bits to 48
 * Enable 256TB in MMU controller
 * Add additional asserts

Tested on Cavium SoC and two ARM64 Chromebooks.

Change-Id: I89e6a4809b6b725c3945bad7fce82b0dfee7c262
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/24970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-03-23 04:09:50 +00:00
Paul Menzel 4183260304 payloads/seabios: Update stable from 1.11.0 to 1.11.1
SeaBIOS 1.11.1 was released with the changes below.

```
$ git log --oneline rel-1.11.0..rel-1.11.1
0551a4b paravirt: Only enable sercon in NOGRAPHIC mode if no other console
        specified
a7aa43e pci: fix 'io hints' capability for RedHat PCI bridges
0e739f2 shadow: Don't invoke a shutdown on reboot unless in a reboot loop
5d9a515 build: Use git describe --always
```

Change-Id: Ia77e98edcd42b28677de9670ce13c2ea5d327315
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/25284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-03-22 15:28:33 +00:00
Jonathan Neuschäfer e33f120cb8 payloads/external/GRUB2: Build only for supported architectures
GRUB2 doesn't support all architectures that coreboot supports.
Furthermore, coreboot's build script for GRUB2 doesn't support all of
these architectures.

Let the user select GRUB2 only when building for x86 and ARM, which are
known to work.

Change-Id: I5ef2020b2acb4cd008a57a2372734674f8b84a36
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20 23:16:05 +00:00
Julius Werner 3faa2c802e libpayload: usbhid: Zero-initialize all parts of usbhid instance struct
The USBHID driver zero-initializes some but not all of the fields in its
usbhid_inst_t structure. This is a problem because under some
circumstances, some of the uninitialized fields may be read and lead to
incorrect behavior. Some (broken) USB keyboards keep sending reports
that contain all zeroes even when they have no new keys... these usually
get silently ignored, but if the usbhid_inst_t structure is in an
inconsistent state where 'previous' is zeroed out but 'lastkeypress'
is non-zero because it wasn't properly initialized, these reports will
be interpreted as keyrepeats of the bogus 'lastkeypress'. This patch
changes the code to just xzalloc() the whole structure so we won't have
to worry about initialization issues anymore.

Change-Id: Ic987de2daaceaad2ae401a1e12b1bee397f802ee
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-02-16 00:08:26 +00:00
Gergely Kiss af15268c10 tianocore: fix Makefile to build a custom revision or branch
Kconfig variables TIANOCORE_REVISION and TIANOCORE_REVISION_ID
do not have an effect without this fix, the build process would
checkout the hard-coded stable hash even if these variables are set.

Change-Id: I9711a370eeade3cba0a9e127deb3d96d82adc512
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/22983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-15 18:30:23 +00:00
Arthur Heymans 47dd96db97 payloads: Add an option to compress secondary payloads
Both GRUB and SeaBIOS can chainload lzma compressed payloads.
Therefore it is beneficial to compress secondary payloads
like Memtest86+, coreinfo, nvramcui,... for both size reasons and
often also speed reasons since the limiting factor is generally the
IO of the boot device.

Tested with SeaBIOS and memtest86+ master on Thinkpad X220.

Change-Id: Iddfd6fcf4112d255cc7b2b49b99bf5ea4d6f8db4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-10 23:57:06 +00:00
Matt DeVillier f18c0415ef payload/tianocore: Fix patch to preserve coreboot table
Part of the original patch, commit 85a90e1, reverted edk2 commit:
1d7258f [CorebootModulePkg:Removing EFI_RESOURCE_ATTRIBUTE_TESTED]
which had the unintended effect of causing memory above 2GiB
from being unavailable (marked reserved) when booting without a
connected display (aka headles mode).

This commit strips the patch to only the component needed to fix
reading of the coreboot table low memory pointer.

TEST: boot 4GB google/panther without connected display, verify
memory above 2GB available via 'dmesg | grep BIOS-e820' and 'free -m'

Change-Id: I39327929f9b0b940fc12cdca1d744456fdc097e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-02-01 19:31:24 +00:00
Arthur Heymans 85a2c71550 payloads/tianocore: Add a patch to use the proper BytesPerscanline
This fixes tianocore garbled framebuffer when 'x_resolution *
bits_per_pixel / 8' is not equal to 'bytes_per_line'.

This patch was also send to the edk2-devel mailing list:
https://lists.01.org/pipermail/edk2-devel/2018-January/020436.html

Tested on Thinkpad X220 with libgfxinit on 1366x768 display.

Change-Id: Ib9eaf692f86d416cd4ec3cc73a8b0aa0a28a38dd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2018-02-01 18:57:52 +00:00
Aaron Durbin 610e2e6faf libpayload: allow x86 devices to provide non-tsc implementation
Make is so that a different timer source can be provided instead
of TSC on x86 platforms.

BUG=b:72378235,b:72170796

Change-Id: I6faeecf7624a5aa4e1af8862036f1fbd2f54eb51
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-26 00:23:28 +00:00
Martin Roth a2fc1aee44 payloads/nvramcui/payload.sh: Fix shellcheck warnings
In payloads/nvramcui/payload.sh line 5:
DIR=`dirname $0`
    ^-- SC2006: Use $(..) instead of deprecated `..`
             ^-- SC2086: Double quote to prevent globbing and word \
                 splitting.

In payloads/nvramcui/payload.sh line 6:
lpgcc -o $DIR/nvramcui.elf $DIR/nvramcui.c 2>&1 >/dev/null || exit 1
         ^-- SC2086: Double quote to prevent globbing and word \
             splitting.
                           ^-- SC2086: Double quote to prevent \
                               globbing and word splitting.
                                           ^-- SC2069: The order of \
                                                of the 2>&1 and the \
                                                redirect matters. The \
                                                2>&1 has to be last.

Change-Id: Iceab2d0df49c642f54e6b911793aa1479f542644
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-24 23:01:35 +00:00
Martin Roth c0c2d457a5 payloads/depthcharge: Update stable version upstream master
Updating from commit id f3bb31fee:
2017-09-08 (vboot: Support EC early firmware selection)

to commit 61cfcc3b:
2018-01-17 (meowth: Select CONFIG_DRIVER_BUS_SPI_INTEL_GSPI_VERSION_2)

This brings in 57 new commits.

Change-Id: Iadacc6017abbcc659e461d2fc27990ef8124871b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23 22:58:10 +00:00
Arthur Heymans 30a6b74f99 payload/Kconfig: Use LZMA by default
With the tianocore payload on a Thinkpad X200 the filesize increased
by approximately 50% and the time to fetch and decompress the payload
increased by approximately %300 , so something is definitely wrong
with it and it shouldn't be used as the default compression method.

Change-Id: I9661c82750104d737596e7b3a8974324765938a5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-22 14:45:27 +00:00
Antonello Dettori fbcfdaf785 payloads: add support lz4 compression
Add the option to use the lz4 compression method
to compress payloads.
Also sets LZ4 as the default compression method.

Change-Id: Ic712f984f791d268440c8463eaea0d246aa31d99
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/15817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15 01:27:48 +00:00
Philipp Deppenwiese d8b4139bca payloads/SeaBIOS: Add different MMIO uart configurations
The MMIO address can change for different platforms
like Apollolake.

Change-Id: I6ec72d3a14f00212323a04e20d5a477dbc26b770
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-20 16:39:50 +00:00
Nico Huber 4792689f67 libpayload: Add pci_free_dev() and some boilerplate
Add just enough code and boilerplate to keep it compatible with future
libflashrom.

Change-Id: If0d46fab141da525f8f115d3f6045a8c417569eb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07 21:51:24 +00:00
Nico Huber 45ccab3352 payloads/external/Makefile: Add missing dependency
The depthcharge .config only exists after depthcharge was built. Other
possible `PAYLOAD_CONFIG` files most probably miss a rule, too.

Change-Id: I8e6f79bb2bd07cbef1317f2623bbef9ca0e74880
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/22137
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07 19:28:44 +00:00
Julius Werner f38a10f8d2 libpayload: Add SKU ID coreboot table support
This patch adds support to read the SKU ID entry from the coreboot table
that was recently added in coreboot.

Change-Id: I1c3b375da6119a4f8e8e7e25a11644becb90f927
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22743
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07 01:19:38 +00:00
Julius Werner 2e029ac6a6 libpayload: Minor board ID / RAM code cleanups
This patch mirrors recent cleanups in coreboot regarding the strapping
ID entries in the coreboot table.

Change-Id: Ia5c3728daf2cb317f8e2bc72c6f1714d6cb4d080
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07 01:18:30 +00:00