Commit Graph

21 Commits

Author SHA1 Message Date
Jonathan A. Kollasch a1114f608b autoport: Add Xeon E3-1200 v2 memory controller ID
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Change-Id: Ic5f18669a04397f570d49c1ff056cd90b3eb04a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-14 17:02:30 +00:00
Angel Pons 6779d2352c util/autoport: correct build errors of produced files
Change-Id: I8d1a6af6f1d70268f17692bee130c08502082c97
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-08 14:25:23 +00:00
Nico Huber 772a154d39 nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGE
We keep the support, though. Just now that `libgfxinit` is fixed, we
don't need the distinction anymore. Causally, we also don't need
CPU_INTEL_MODEL_306AX any more.

TEST=Played tint on kontron/ktqm77. Score 606

Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-12 15:03:03 +00:00
Angel Pons 08caa792e6 util/autoport: Trim gfx.did to size
Since the values are hardcoded, we might as well hardcode values that
make sense.

Change-Id: I3ac0e2d74a42c1fe55b1cdc3e2a970ae80cc9f37
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30963
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18 09:20:05 +00:00
Alexander Couzens 96a437f4aa util/autoport: remove obsolete symbol SANDYBRIDGE_IVYBRIDGE_LVDS
This symbol was removed in
a6be58fece ("nb/intel/sandybridge: Remove the C native graphic init")

Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: I87801552e1c37162897949ec0db3904f850f0bfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-14 11:25:47 +00:00
Angel Pons 8296fdd979 util/autoport: Separate NB and SB PCIe port IDs
The root port IDs on bd82x6x.go were for both the PCH and the CPU PCIe
root ports. Put the latter on sandybridge.go instead, and add missing
IDs.

Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30962
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13 09:48:40 +00:00
Arthur Heymans 7e6946a74c cpu/intel/model_206ax: Remove the notion of sockets
With the memory controller the separate sockets becomes a useless
distinction. They all used the same code anyway.

UNTESTED: This also updates autoport.

Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31031
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24 13:39:19 +00:00
Angel Pons 6541956e97 util/autoport: Break very long line
Change-Id: Id45b0970a457ad4a724b71b4887ce4a1332596be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30968
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18 20:46:16 +00:00
Angel Pons 07b6f16063 util/autoport: Correct DSDT include statement
With commit aaced4a (cpu/intel/common: Use a common acpi/cpu.asl file),
some model_206ax code was moved to a common place. However, autoport
was not updated accordingly.

Change-Id: I51b7e9c5d226f591596c33d6a3cb326a34420493
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30967
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18 19:36:13 +00:00
Angel Pons cea8493285 southbridge/intel/bd82x6x/Kconfig: Do not include any IFD by default
Since only a handful of boards have descriptor blobs in the tree, it makes no
sense to have `HAVE_IFD_BIN` enabled by default then disabled on each mainboard.
This patch flips the default value of said variable, rendering all current
overrides unnecessary. The few boards which have an IFD in the blobs repo use
`select HAVE_IFD_BIN` to enable adding the IFD by default.

Since `HAVE_ME_BIN` depends on `HAVE_IFD_BIN`, the former has been removed
alongside the latter, and has been added to the boards with a ME blob as
`select HAVE_ME_BIN`.

Both `HAVE_IFD_BIN` and `HAVE_ME_BIN` have been removed from autoport as well.

Change-Id: I330c4886f8bea4b1a8ecad6505a0e5cc381654d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-05 19:57:56 +00:00
Nico Huber 23b93dd7d8 intel/sandybridge: Clean VGA BIOS ids up a little
Sync map_oprom_vendev() and autoport with the list of PCI ids in the
`gma.c` driver, remove one obsolete Kconfig default override.

Change-Id: I12f24f415b695c516fbb947114e09c873af2e439
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-07-30 00:07:01 +00:00
Nico Huber 2b5c021431 intel/sandybridge: Gather MMCONF_BASE_ADDRESS defaults
All affected boards did the same USE_NATIVE_RAMINIT distinction or
actually selected USE_NATIVE_RAMINIT. Also update autoport.

Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20813
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-07-30 00:06:51 +00:00
Omar Pakker ecf3489df8 util/autoport: Add the PCI ID of the iGPU for the Intel i7 3770K
This adds one of the Xeon labeled PCI IDs used in Sandy-/Ivy Bridge
generation processors. This ID is used by the non-Xeon i7 3770K.

Change-Id: Iad7745136efeb10ff745001413f4ccb6488b5ec0
Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/19516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-05-03 20:14:05 +02:00
Iru Cai 8e7928a6fe sandybridge/gma_lvds: support both Sandy&Ivy on one board
Sandy and Ivy Bridge processors use the same socket, and a mainboard
with the socket can support both types of CPUs. However, they use
different native graphics init code for LVDS and cause a crash if
running the wrong code.

This change detects the CPU type and then selects the right code to
run. It will add some more code in ramstage. It also merges the
{SANDY,IVY}BRIDGE_LVDS symbol to one SANDYBRIDGE_IVYBRIDGE_LVDS.

Tested on a Lenovo T520 with i7-2630qm and i7-3720qm

Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91
Reviewed-on: https://review.coreboot.org/12087
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
2016-03-05 09:39:41 +01:00
Vladimir Serbinenko 144eea0697 Make MRC vs native a config rather than making a separate chipset for it.
Tested by making lenovo x230 configurable despite pretty MRC bugs.

Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13658
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12 17:09:05 +01:00
Vladimir Serbinenko b2eea81992 sandybridge: Set all native gfx-related options in northbridge code.
In the same time remove few native gfx options which were improperly set
and only added dead code to the binary.

Change-Id: I4ed3fec03a1655ae0a779c3aa3845de273cb12e1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13649
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-02-09 22:35:09 +01:00
Nico Huber 954a55b950 gma ACPI: Make brightness levels a per board setting
Those are actually board specific. Keep the old value as defaults,
though. The defaults are included by all affected boards.

Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11705
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-10-22 23:01:36 +02:00
Vladimir Serbinenko c48f5ef3cc Kill lvds_num_lanes
Only one value would work with corresponding gma code currently (which one
depends on board). Going forward, it's possible to compute which number can
be used, so there is no need to keep this info around.

Change-Id: Iadc77ef94b02f892860e3ae8d70a0a792758565d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11862
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-10-11 10:07:17 +00:00
Vladimir Serbinenko 551cff08d5 Derive lvds_dual_channel from EDID timings.
Based on the info by Felix Held.

Change-Id: Iab84dd8a0e3c942da20a6e21db5510e4ad16cadd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11857
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-10-11 10:07:12 +00:00
Alexandru Gagniuc ecf2eb463f sandybridge ivybridge: Treat native init as first class citizen
This is a sad story. We have three different code paths for
sandybridge and ivybridge: proper native path, google MRC path, and,
everyone's favorite: Intel FSP path. For the purpose of this patch,
the FSP path lives in its own little world, and doesn't concern us.

Since MRC was first, when native files and variables were added, they
were suffixed with "_native" to separate them from the existing code.
This can cause confusion, as the suffix might make the native files
seem parasitical.

This has been bothering me for many months. MRC should be the
parasitical path, especially since we fully support native init, and
it works more reliably, on a wider range of hardware. There have been
a few board ports that never made it to coreboot.org because MRC would
hang.

gigabyte/ga-b75m-d3h is a prime example: it did not work with MRC, so
the effort was abandoned at first. Once the native path became
available, the effort was restarted and the board is now supported.

In honor of the hackers and pioneers who made the native code
possible, rename things so that their effort is the first class
citizen.

Change-Id: Ic86cee5e00bf7f598716d3d15d1ea81ca673932f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11788
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-10-03 22:22:54 +00:00
Vladimir Serbinenko 3129f792f7 autoport: Write autoport together with porting guide for sandy/ivybridge.
This should be able to generate bootable ports for sandy/ivy, possible with
minor fixes. Howto is in readme.md

Change-Id: Ia126cf0939ef2dc2cdbb7ea100d2b63ea6b02f28
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7131
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-29 11:26:29 +02:00