Commit Graph

32411 Commits

Author SHA1 Message Date
Edward O'Callaghan 731e6288e6 mainboard/google/puff: Enable net driver on pcie ep
Let coreboot know there is a NIC device on the end so
that the mac from vpd is set at early boot.

Properly configure the link-leds in devicetree s.t.
valid values are written out to the register at initialization.

BUG=b:146592075,146999042,146999043
BRANCH=none
TEST=Boot to kernel.
     Insert mac address into VPD
       vpd -s ethernet_mac=<address>
     reboot the system.
     Ensure we have ip address and corresponding mac
     address with ifconfig.
     Ensure ethernet controller shows up with lspci.

Change-Id: I76ce6d8a5a26842fcb2544ee96567fe0da8603b1
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2020-01-02 04:18:28 +00:00
Felix Held ef4fe3e37c nb/intel/sandybridge: replace .val_4028 with .io_latency
Change-Id: Id584028e99975f18c97780ca6b3c7988d9e84f45
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38027
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-01 16:12:32 +00:00
Angel Pons 26be0bdbf6 nb/intel/sandybridge/sandybridge.h: Do cosmetic fixes
Change-Id: I212f58bdaee538ad8f0197c0aec742aace1c7921
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-01 16:10:54 +00:00
Angel Pons 3473f76e90 nb/intel/sandybridge: Use the MC_BIOS_DATA define
Change-Id: I177f419d2675ebda5c231a257bed8baf56e13291
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-01 16:10:36 +00:00
Angel Pons 2a9a49b7ba nb/intel/sandybridge: Make `PM_PDWN_Config` uppercase
Change-Id: Id37d2367d57ff925476c53bb0edab927c1c768f6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-01 16:10:10 +00:00
Felix Held 50b7ed2bbe nb/intel/sandybridge: add and use memory thermal configuration registers
Change-Id: I96efeadcc7d22bc8453645f6a0884d82edf3aec6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-01 16:09:51 +00:00
Felix Held f54ae3875f nb/intel/sandybridge: add and use ME stolen memory and lock bit defines
Change-Id: If4663498b10a5eedcc1aa51088b984ecc49ef23e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-01 16:09:39 +00:00
Felix Held 7c09c6a960 nb/intel/sandybridge: remove unused duplicate PCIEXBAR define X60BAR
Change-Id: Ie5a28ceb3d1b684b9c94dcae5b303a4dce75f273
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-01 16:09:16 +00:00
Felix Held dee167ee39 nb/intel/sandybridge: add and use more MCHBAR register defines
Change-Id: Ie0a9be0899830a2bf9a994d10c417b0968d1cd47
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-01 16:09:00 +00:00
Felix Held 85e1491eba nb/intel/sandybridge: move MCHBAR register definitions to sandybridge.h
Change-Id: Ibce9f043d3b3fa9acd297f4130bda7a3c595aaa0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-01 16:08:45 +00:00
Felix Held 651f99f12b nb/intel/sandybridge: use MESEG register names from datasheet
I used register names guessed on what the registers do, since the SNB
documentation marked those registers as reserved; the IVB documentation
(326765-005) has names for the registers, so I'll use those.

Change-Id: I2f1194438a56546d9836dd12635d064a900a2fd8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38008
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-01 16:08:32 +00:00
Angel Pons 6ad0ab1a69 mb/**/acpi: Remove unused files
Remove commented-out entries in dsdt.asl, and then remove files that do
not get built.

Change-Id: I579e7ffbc2d6596fd7ffe6863ff3b3fb14b0ade6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-31 18:57:16 +00:00
Kyösti Mälkki e3d9d67e99 device: Log times with millisecond resolution
To print times with 1 us resolution just adds unnecessary noise
when comparing logs across different boots. Furthermore, just
the printk itself is 1 ms if some slow console is enabled.

Change-Id: Ibea43124a1937f404a6e71fd9431086b2b72290a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-31 17:38:22 +00:00
Kyösti Mälkki 94694a810e console,boot_state: Reformat state times output
For each boot_state, report the times spent interleaved
with other console output and remove the samples arrays.

The time spent to report the times to console is not
accounted for.

Change-Id: I0c847da98901c56b356b4a933d9ae865dada98b6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-31 17:38:04 +00:00
Elyes HAOUAS 99b075aa94 nb/amd: Fix typo
Change-Id: I7d27981dd7af53f0e8484d267a9a40fd3d269212
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-31 15:24:06 +00:00
Elyes HAOUAS 5bca34193d src/{soc,southbridge}/amd: Fix typo
Change-Id: I7e3dc64648af05d51a319019397f24ba74c25c37
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-31 15:23:55 +00:00
Elyes HAOUAS e29c70dea1 sb/amd/cimx/sb800/cfg.c: Fix typo
Change-Id: I46653d9530a136a56b762858de2bae2c7cbfd461
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-31 15:23:29 +00:00
Jacob Garber 4a216475f5 src: Remove some romcc workarounds
Now that romcc is gone, move cmos_post_init() into post.c, and remove
some preprocessor workarounds.

Change-Id: I0ee4551e476cdd1102e86e7efc74d5909f64a37b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-31 15:22:43 +00:00
Peter Lemenkov d225834220 mb/*/*/acpi_tables: Don't initialize already initialized fields
Don't initialize fields with zeroes since gnvs structs were zeroed out
in southbridge already. See

* src/southbridge/intel/*/lpc.c

Change-Id: I5228f2cdc94df722ffa687c45b4e4fd25e82df82
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-31 15:21:19 +00:00
Peter Lemenkov 2450a7e724 mb/*/*/acpi_tables: Don't zero out gnvs again
The gnvs structure was zeroed out before calling acpi_create_gnvs(...)
in the following files:

* src/southbridge/intel/*/lpc.c

Change-Id: Id7755b1e4b8f5cb8abd1f411b5dc174b6beee21c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37956
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31 15:21:11 +00:00
Bill XIE 2e5f1f7e94 mb/hp: Add data.vbt files for folio_9470m and revolve_810_g1
Extracted from live running machines running vendor firmware.

Change-Id: I5082af9349c25a5f1759ba00b3fbf8d18f8fde4d
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-31 15:19:49 +00:00
Bill XIE 9594550452 ec/hp/kbc1126: Make firmware offsets user configurable
After C_ENVIRONMENT_BOOTBLOCK became mainstream, coreboot build system
starts to produce larger bootblock, conflicting with former default
offsets.

This change makes these offsets configurable before building, with
default values lower than before, to better fit the larger bootblock.

Change-Id: Ie022663a4d0df7f431865b55f7329a9ebb90863b
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37778
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31 15:19:41 +00:00
Matt DeVillier 76ea54e962 mb/google/atlas: Add libgfxinit support
Add Kconfig, panel delays extracted from VBT (and confirmed by Linux)

Test: build/boot Atlas with libgfxinit and Tianocore payload

Change-Id: I94c227cd4f020db719bf81118d983493752bb00f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37989
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31 15:18:17 +00:00
Matt DeVillier f41eea4c0c mb/google/peppy: Add Hynix memory HMT425S6CFR6A support
Adapted from Chromium commit b8dcb1a [Peppy: Update Memory IDs]

Add Hynix memory HMT425S6CFR6A support.
RAM_ID: 011 4GB Hynix HMT425S6CFR6A
RAM_ID: 111 2GB Hynix HMT425S6CFR6A

Original-Change-Id: I26d5c4ad00509e7823c325ee8391e0b18fee44d8
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1074849
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: David Wu <david_wu@quanta.corp-partner.google.com>

Change-Id: I4d165f61b8a13e5ed025e9ddbc4330db88e2fa3d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-31 15:18:05 +00:00
Matt DeVillier 66bd887005 mb/google/peppy: add _DSD to touchscreen ACPI
Recent changes to the Atmel touchscreen driver in the mainline
kernel broke functionality with devices running upstream coreboot,
due relying on another driver (chromeos_laptop) which makes the
assumption that the i2c devices are be in PCI mode (as with the
stock Google firmware) rather than in ACPI mode as they are in
upstream coreboot.

Mitigate this by adding the required devicetree property so the
Atmel toushcreen driver will correctly attach without the use
of chromeos_laptop.

Test: build/boot peppy on 4.18+ kernel, verify touchscreen working

Change-Id: I05df8367886eef55b409590f75a68d98d4e5fbdf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolò
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-31 15:17:51 +00:00
Meera Ravindranath 48c7870e52 soc/intel/{icl,cnl,tgl}: Always add PM1_TMR block to FADT
Provide the PM1_TMR information in the FADT even if PmTimerDisabled is
set because PM timer emulation is enabled via MSR 121h so the timer will
still work and can be used by things like Tianocore and Windows.

Porting from 662b6cb3ed (soc/intel/skylake: Always add PM1_TMR block to FADT).

Change-Id: Ie3d592623f3a84051477ffe83a0cf0daf30dd36f
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-31 15:17:27 +00:00
Angel Pons 408d1dac9e mb/**/dsdt.asl: Remove outdated sleepstates.asl comment
Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.

Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-31 15:16:57 +00:00
Peichao Wang ae863e2e25 mb/google/hatch/akemi: modify DPTF parameters for new FAN
New FAN use NTN bearing, so tune DPTF parameters to satisfy
requirement

BUG=b:144370669
TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec
chromeos-bootimage

Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6fbf0c80cd2421ce9a489c8923a97d860a11b545
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-12-31 15:15:26 +00:00
Elyes HAOUAS 959f406bf3 sb/i82801gx/nvs: Add missing <stdint.h>
Change-Id: I22b3fb31d8694c76b4a6fdfa40a72977e9099815
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37899
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31 08:05:14 +00:00
Elyes HAOUAS 748caed022 northbridge: Add missing include <device/pci_def.h>
Change-Id: Ib63835d2407bbabbd78b43927f7fbd407ca06a08
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37841
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31 07:42:30 +00:00
Elyes HAOUAS 536799d5f6 sb/amd/cimx/sb800: Remove unused BOOTBLOCK_SOUTHBRIDGE_INIT
Change-Id: Ie0dc165076644e225064568b4cb6f73b2af66438
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-30 10:19:31 +00:00
Felix Held 734c999637 ibase/mb899: use common winbond/nuvoton HWM bank select function
Change-Id: I7f159074c25a0fdfe2ee15024c1ed6c062ce75d5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-30 02:57:37 +00:00
Felix Held 35103fd961 kontron/986lcd-m: use common winbond/nuvoton HWM bank select function
Change-Id: I169b16c99a864ecff54112bcc073f2c141c2009f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-30 02:57:28 +00:00
Felix Held 15b6c4af63 superio/nuvoton: add common HWM bank select function
Change-Id: I828b6caa37e52c13e1876c7ca4edbd171e70d3f7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37945
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-30 02:57:13 +00:00
Johanna Schander d756c27a54 util/inteltool: Add chip detection for IceLake chips
Change-Id: Ia4752391e1232ac67d8927778a3a94eec5c68410
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37986
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Christoph Pomaska <github@aufmachen.jetzt>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-29 21:13:17 +00:00
Felix Held 8fa02a8ef9 nb/intel/sandybridge: simplify ME lock and memory enable bit write
Timeless build results in identical image for X230.

Change-Id: I36842ebd4917e96aa8aec87ba13d27bd4bf44b76
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-29 12:20:16 +00:00
Felix Held bc3668a468 nb/intel/sandybridge: add and use defines for ME base and mask registers
Timeless build results in identical image for X230.

Change-Id: Ia2bd26b97cb2ae77f29d8978f62d2f6be12b43e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-29 12:19:43 +00:00
Felix Held 4902fee441 nb/intel/sandybridge: add and use defines for PCI_DEV(0,0,0) registers
This patch didn't change the resulting binary for an X230 when using
TIMELESS_BUILD=1

Change-Id: Ibeb10c3e0c04dec76892a86fa39e60543b2ee2f5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-29 12:19:14 +00:00
Rizwan Qureshi cf425783c8 ec/google/chromeec: ignore LIMIT_POWER based on command code in response
Assume that LIMIT_POWER is not requested if the ec does not support it.
Do this by checking the command code in the response message instead
of return value.

BUG=b:146165519
BRANCH=None
TEST=Boot puff with EC which does not support LIMIT_POWER param.

Change-Id: Ib2f5f69a53f204acebfab3e36aab2960eeec1204
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-12-29 00:34:21 +00:00
Peter Lemenkov a76cf28279 mb/lenovo/*/acpi_tables: Don't initialize already initialized fields
Don't initialize fields with zeroes since gnvs structs were zeroed out
in southbridge already.

Change-Id: I2ccf4699ba3ed3f5b9402c0340153d4a5bf82682
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-28 09:56:50 +00:00
Patrick Georgi 0acfe1c8cd util/testing: Remove romcc from testing
Change-Id: If90193dc7c85133b10082c68a6cec6c1b0b35ffb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37958
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-28 09:45:12 +00:00
Marshall Dawson 5b9062f3f6 soc/amd/common: Correct SPI FIFO size check
When checking that command and data fit in the FIFO, don't count the first
byte.  The command doesn't go through the FIFO.

TEST=confirm error (4+68>71) goes away on Mandolin
BUG=b:146225550

Change-Id: Ica2ca514deea401c9c5396913087e07a12ab3cf3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-27 17:15:19 +00:00
Martin Roth 92bc83674b util/docker/coreboot-sdk: Add libcurl4 requirements for em100
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia1cd7e12f12cb6d26a10fd358a3b32c31ce1c834
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-12-27 17:09:41 +00:00
Bora Guvendik d6db845f01 dram-spd: Remove free()
free() is not needed since the memory is not dynamically allocated.

Change-Id: I90659722aaca6ced1e1cbc3db4180b0811205e95
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-27 16:08:40 +00:00
Peter Lemenkov 9fadd9a917 mb/lenovo/*/acpi_tables: Don't zero out gnvs again
The gnvs structure was zeroed out already in the following files:

* src/southbridge/intel/i82801ix/lpc.c (t400 and x200)
* src/southbridge/intel/i82801gx/lpc.c (thinkcentre_a58)

Change-Id: Id7d552e1c4084a0b36b98f9627a85a75c8b90e81
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-27 09:09:20 +00:00
Peter Lemenkov 6c2c018e15 mb/*/*/acpi_tables: Remove unnecessary function call
Remove acpi_update_thermal_table local function.

Change-Id: I4857348088feb8eaf1dd7f553c4efb29da8943cf
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-27 09:09:02 +00:00
Paul Fagerburg 1fe7dcb047 util/mainboard/google: add support for Volteer
create_coreboot_variant.sh now supports the Volteer baseboard in
addition to Hatch. The shell script and supporting python code are
moved up one level, while retaining the ${BASE}/template/* file
structure for each supported baseboard.

kconfig.py has to add slightly different text to Kconfig.name
depending on which baseboard is selected.

BRANCH=None
BUG=b:146646594
TEST=Create variants of Hatch and Volteer, check that the staged
commits are correct.

$ ./create_coreboot_variant.sh hatch sushi b:12345
src/mainboard/google/hatch/Kconfig and Kconfig.name will have new
sections for SUSHI. src/mainboard/google/hatch/variants/sushi
will have a copy of util/mainboard/google/hatch/template

$ ./create_coreboot_variant.sh volteer ripto b:12345
src/mainboard/google/volteer/Kconfig and Kconfig.name will have new
sections for RIPTO. src/mainboard/google/volteer/variants/ripto
will have a copy of util/mainboard/google/volteer/template

Also run the script with an existing board name to verify that you
can't create a variant that already exists.

Change-Id: I084b6c50bb76af0d11dc86a96b3c3c434569a0dd
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
2019-12-27 09:03:48 +00:00
Seunghwan Kim f71991edc3 mb/google/kohaku: Update reset_delay_ms for digitizer device
We found the driver binding failure issue could be cleared with 100ms
of "reset_delay_ms". Needs further check with device vendor, anyway it
seems the IC need some time before communication after de-assertion of
reset.

BUG=b:129159369
BRANCH=firmware-hatch-12672.B
TEST=Verified driver bound successfully.

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: Iccb33c13c9a390a2c971325c74c0c4ad4b08618e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-27 09:03:15 +00:00
Kyösti Mälkki d60e9ab74e cpu/intel/microcode: Apply more strict guard for assembly files
Change-Id: I8243be7c9a57402b2ac1cfa1c0552990d4a4ba74
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-27 09:01:50 +00:00
Kyösti Mälkki 405812209d arch/x86: Remove <arch/cbfs.h>
There are no symmetrical headerfiles for other arch/ and
after ROMCC_BOOTBLOCK and walkcbfs() removal this file
ended up empty.

Change-Id: Ice3047630ced1f1471775411b93be6383f53e8bb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-27 09:01:12 +00:00