Commit Graph

18123 Commits

Author SHA1 Message Date
Lee Leahy 2a8cc3064e Documentation/Intel/Board: Add analog switch link
Add link for TI TS5A23159 specification.

TEST=None

Change-Id: I2756ded963fc7597e4db1fa151bf62630b1108d9
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15003
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 22:02:03 +02:00
Lee Leahy d5493683ea soc/intel/quark: Conditionally define BIT names
Only define BIT names if they are not already defined.

TEST=Build and run on Galileo Gen2

Change-Id: Ief4c4bb7a42a1bb2a7f46f13dc9b8bbb4d233e3c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15002
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 22:01:27 +02:00
Lee Leahy 5e808cb811 mainboard/intel/galileo: Split out enabling FSP1_1
Split out enabling FSP 1.1 support to prepare for enabling FSP 2.0
support.

TEST=Build and run on Galileo Gen2.

Change-Id: Ic4e814bcf61f9480f98e2d7bc7a1648dec43a07d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15001
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 22:00:30 +02:00
Lee Leahy 6b24dfce74 soc/intel/quark: Fix reg_script display
Remove extra ": " following reigster type.

TEST=Build and run on Galileo Gen2

Change-Id: I57dd40a540d7b5371a6c45174f47a311b83a2aab
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14948
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 21:59:47 +02:00
Lee Leahy 7f4b053980 soc/intel/quark: Clear SMI interrupts and wake events
Migrate the clearing of the SMI interrupts and wake events from FSP into
coreboot.

TEST=Build and run on Galileo Gen2

Change-Id: Ia369801da87a16bc00fb2c05475831ebe8a315f8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14945
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 21:57:55 +02:00
Lee Leahy 773ee2bb17 soc/intel/quark: Rename pmc.c to lpc.c
Rename the file pmc.c to lpc.c to prepare for further additions.

TEST=Build and run on Galileo Gen2

Change-Id: If98825d72878f0601f77bff8c766276dbda8a9ae
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14946
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 21:56:08 +02:00
Lee Leahy 5ef051a53a soc/intel/quark: Add PCIe reset support
Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into
coreboot.

Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14944
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 21:50:31 +02:00
Matt DeVillier a87fcabd2e google/ninja: Upstream AOpen Chromebox Commerical
Migrate google/ninja (AOpen Chromebox Commerical) from Chromium tree to
upstream, using google/rambi as a reference.

original source:
branch firmware-ninja-5216.383.B
commit 582a393 [Ninja, Sumo: Add SPD source for Hynix H5TC4G63CFR-PBA]

TEST=built and booted Linux on ninja with full functionality

blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.elf)
external reference code (refcode.elf)

Change-Id: I0f1892c24c08fa2d53185b2cf8b6f5a9001b2397
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/14950
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31 21:15:27 +02:00
Jonathan Neuschäfer 4acb0e7742 commonlib/lz4: Avoid unaligned memory access on RISC-V
From the User-Level ISA Specification v2.0:

   "We do not mandate atomicity for misaligned accesses so simple
    implementations can just use a machine trap and software handler to
    handle misaligned accesses." (— http://riscv.org/specifications/)

Spike traps on unaligned accesses.

Change-Id: Ia57786916f4076cc08513f4e331c2deec9cfa785
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14983
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31 21:07:03 +02:00
Jonathan Neuschäfer 0a54fb533d lib/hardwaremain: Add \n to "Boot failed" message
Change-Id: I106fccd725a5c944f4e8e0f196b31c9344f588c7
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14984
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31 20:20:44 +02:00
Andrey Petrov 204af8157d soc/intel/apollolake: Update SPI memory mapping constraints
MMIO region of 256 KiB under 4 GiB is not decoded by SPI controller
by hardware design. Current code incorrectly specifies size of that
region to be 128 KiB. This change corrects the value to 256 KiB.

Change-Id: Idcc67eb3565b800d835e75c0b765dd49d1656938
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14979
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-05-31 20:06:29 +02:00
Damien Zammit b28a411362 mb/gigabyte/ga-g41m-es2l: Update board_info.txt and add item to Kconfig
This adds the website URL to the board info and also enables
the realtek nic reset function as per a previous patch.

Change-Id: I2cda120c59b55f0dd2ffa78d397b16beb13d6843
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/14954
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 20:04:14 +02:00
Damien Zammit e983f0cb4b drivers/net/r8168: Add driver for realtek nic
One thing that is vital to this patch is the MAC address setting
in case the EEPROM/efuse is unconfigured.
Linux now recognises the default MAC address on GA-G41M-ES2L which
does rely on the default bios settings for the MAC address.

Change-Id: I32e070b545b4c6369686a7087b7ff838d00764e3
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/14927
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 20:03:39 +02:00
Damien Zammit 2abd3f9e1c mb/gigabyte/ga-g41m-es2l: Use x4x_late_init()
This patch adds DMI/EP init to the board and fixes
a couple of minor things.

Change-Id: I10d0f6ce747b60499680e4dc229b7fcbb16cc039
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/14926
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 20:02:55 +02:00
Damien Zammit a090ae04c2 nb/intel/x4x: Add DMI/EP init
The values were obtained from vendor bios at runtime.
I am not 100% sure of the sequence required to initiate them,
but guessed from the gm45 code.  There may be some status bytes
needed to be polled during the sequence that is missing,
but as I don't have bios writer's datasheet it's very hard
for me to know.

Change-Id: Idd205e0bab5f75e01c6e3a5dc320c08639f52db8
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/14925
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 20:02:09 +02:00
Damien Zammit 2b2f465fcb mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA
Previously, due to a bug in devicetree and incorrect IRQ
settings in ACPI, SATA controller would not initialize
any HDDs in the OS, even though it worked in SeaBIOS.
The devicetree setting is not needed because SATA must
function in "plain" mode on this board, as "combined" mode
does not work at all.

Change-Id: I0036c4734de00b84cc3d64f38e4b1fd80fd1a25d
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/14776
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31 20:01:41 +02:00
Duncan Laurie b25a45ca46 skylake: Add SD card device to configure card detect GPIO
Add a PCI driver for the skylake SD card device and have it generate
an entry in the SSDT for the card detect GPIO if it is provided by the
mainboard in devicetree.

This sets up a card detect GPIO configuration that will trigger an
interrupt on both edges with a 100ms debounce timeout and can wake the
SD controller from D3 state.

The GpioInt() entry is bound to the "cd-gpio" device property which will
be consumed by the kernel driver.

The resulting ACPI output in the SSDT will be combined with the SDXC
device declaration in the DSDT.

Example:

Scope (\_SB.PCI0.SDXC)
{
  Name (_CRS, ResourceTemplate () {
    GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 10000,
             "\\_SB.PCI0.GPIO", 0, ResourceConsumer) { 35 }
  })
  Name (_DSD, Package () {
    ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
    Package () {
      Package () { "cd-gpio", Package () { \_SB.PCI0.SDXC, 0, 0, 1 } }
    }
  })
}

Change-Id: Ie4c1bfadd962cf55a987edb9ef86e92174205770
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14995
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31 18:46:39 +02:00
Duncan Laurie 98d69c0627 skylake: Cleanup formatting in pci_devs.h
Minor cleanups in pci_devs.h for indentation and newlines to be
consistent throughout the file.

Change-Id: I522df141a6b33d918cfb3de1b9019c0c4a73e3e5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14994
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31 18:45:40 +02:00
Duncan Laurie 026003e621 skylake: Add Audio DSP device
Add the Audio DSP device for skylake as a PCI driver with a static
scan_bus handler so generic devices can be declared under it.

This is for devices like the Maxim 98357A which is connected on the
I2S bus for data but has no control channel bus and instead just has
a GPIO for channel selection and power down control and needs to
describe that GPIO connection to the OS via ACPI.

Change-Id: Iae02132ff9c510562483108ab280323f78873afd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31 18:45:15 +02:00
Duncan Laurie 0d8bb7427b skylake: Add I2C devices
Add the I2C devices to skylake with the scan_bus handler for SMBUS
devices so that I2C-based devices can be declared in devicetree.cb
and get initialized properly during ramstage.

This does not yet provide the I2C driver, but it allows for devices
that are declared in devicetree.cb to provide ACPI tables to the OS.

Change-Id: I9dfe4a06a8b0bc549a2b0e2d7c033c895188ba30
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14992
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31 18:43:55 +02:00
Duncan Laurie 011533e4c3 skylake: Add GPE header file to chip.h
Add the GPE header file to skylake chip.h so the SOC-defined macros
for the various GPE values can be used in devicetree directly.

For example:
  chip drivers/i2c/touchpad
    register "wake" = "GPE0_DW0_05"
    device i2c 15.0 on end
  end

Change-Id: Ic322108561b34aa34a24a4daba6ba7a4f7a3f9a4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14991
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31 18:43:39 +02:00
Kyösti Mälkki 8f3aaa8a4c Fix leaking CONFIG_VGA=y
Items under DEVICE_SPECIFIC_OPTIONS got selected without
the driver being selected.

Change-Id: I1797fa6175620a9291873559a6308eaea85a090e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14823
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-31 17:18:59 +02:00
Timothy Pearson ca543396a7 mainboard/asus/[kgpe-d16|kcma-d8]: Enable secondary serial port header
The ASUS KGPE-D16/KCMA-D8 have an on-board header for a second RS-232
serial port, however it is disabled by default due to the SuperIO
default pin mux settings.  Enable the secondary serial port early
in romstage to allow use during / after initial boot.

Change-Id: I5b83659dd8b0d6af559c9ceccee55c4cc2f17165
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14892
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-05-31 08:42:23 +02:00
Furquan Shaikh 233f1b6a38 ifwitool: Add new tool for managing IFWI images
- Supports following operations:
 1. add raw/dir sub-partition
 2. extract raw/dir sub-partition
 3. print info
 4. delete raw sub-partition
 5. replace raw/dir sub-partition

Change-Id: I683a0ab13cc50eb60eecca34db4a8ffefc8dccbd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14896
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-30 23:51:42 +02:00
Furquan Shaikh 97d56fa1a2 reef: Remove si-all region from chromeos.fmd
This matches the change in depthcharge fmap.dts to remove si-all
region and mark si-desc as ifd.

CQ-DEPEND=CL:347986
BUG=chrome-os-partner:53689
BRANCH=None
TEST=Compiles successfully

Change-Id: Ic7ed94fcdfb9a79bd6ceb960830f67678b0291b6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14990
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-30 23:50:06 +02:00
Kyösti Mälkki 1716375507 pcengines/apu1: Rename Kconfig variables for pinmux
Add APU1 prefix because Kconfig throws errors if we try to
define the same variables as choice-entry for APU2 board.

Change-Id: Ic071600dd88e391a8a278d63aad13abd01fd3c9d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14988
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-05-30 15:15:24 +02:00
zbao e0849350aa AMD/spi: Do not reset fifo after skipping the sent bytes
After we skip the bytes we send, the fifo pointer is at
right position. Reseting the fifo will change it to a
wrong place.

Please view the flashrom code, which tells the same thing.
https://code.coreboot.org/p/flashrom/source/tree/HEAD/trunk/sb600spi.c#L257

Change-Id: I31d487ce32c0d7ca3dead36d2b14611e73b1ad60
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/14955
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-30 06:09:21 +02:00
Timothy Pearson 69088c2825 sio/winbond/w83667hg-a: Add pinmux defines for UART B
Change-Id: Ib98c69de781d2b651ec168d03250cacc918c5c1f
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/14965
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-05-29 19:34:54 +02:00
Timothy Pearson e4cca16b42 sio/winbond/common: Add function to configure pin mux
Certain mainboards require SuperIO pinmux configuration before
peripherals will become operational.  Allow each mainboard to
configure the pinmux(es) of Winbond chips if needed.

Change-Id: Ice19f8d8514b66b15920a5b893700d636ed75cec
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/14960
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-05-29 19:34:02 +02:00
Furquan Shaikh 161d2334e8 util/cbfstool: Include commonlib/helpers.h in common.h
This avoids re-declaring common macros like ARRAY_SIZE, MIN, MAX and
ALIGN. Also removes the issues around including both files in any
tool.

Also, fix comparison error in various files by replacing int with
size_t.

Change-Id: I06c763e5dd1bec97e8335499468bbdb016eb28e5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14978
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-28 08:48:45 +02:00
Duncan Laurie 559e947306 acpi_device: Add support for writing ACPI Device Properties
The recent ACPI specification extensions have formally defined a
method for describing device information with a key=value format that
is modeled after the Devicetree/DTS format using a special crafted
object named _DSD with a specific UUID for this format.

There are three defined Device Property types: Integers, Strings, and
References.  It is also possible to have arrays of these properties
under one key=value pair.  Strings and References are both represented
as character arrays but result in different generated ACPI OpCodes.

Various helpers are provided for writing the Device Property header
(to fill in the object name and UUID) and footer (to fill in the
property count and device length values) as well as for writing the
different Device Property types.  A specific helper is provided for
writing the defined GPIO binding Device Property that is used to allow
GPIOs to be referred to by name rather than resource index.

This is all documented in the _DSD Device Properties UUID document:
http://uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf

This will be used by device drivers to provide device properties that
are consumed by the operating system.  Devicetree bindings are often
described in the linux kernel at Documentation/devicetree/bindings/

A sample driver here has an input GPIO that it needs to describe to
the kernel driver:

chip.h:
  struct drivers_generic_sample_config {
    struct acpi_gpio mode_gpio;
  };

sample.c:
  static void acpi_fill_ssdt_generator(struct device *dev) {
    struct drivers_generic_sample_config *config = dev->chip_info;
    const char *path = acpi_device_path(dev);
    ...
    acpi_device_write_gpio(&config->mode_gpio);
    ...
    acpi_dp_write_header();
    acpi_dp_write_gpio("mode-gpio", path, 0, 0, 0);
    acpi_dp_write_footer();
    ...
  }

devicetree.cb:
  device pci 1f.0 on
    chip drivers/generic/sample
      register "mode_gpio" = "ACPI_GPIO_INPUT(GPP_B1)"
      device generic 0 on end
    end
  end

SSDT.dsl:
  Name (_CRS, ResourceTemplate () {
    GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionInputOnly,
            "\\_SB.PCI0.GPIO", 0, ResourceConsumer) { 25 }
  })
  Name (_DSD, Package () {
    ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
    Package () {
      Package () {"mode-gpio", Package () { \_SB.PCI0.LPCB, 0, 0, 1 }}
    }
  })

Change-Id: I93ffd09e59d05c09e38693e221a87085469be3ad
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14937
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-28 03:48:55 +02:00
Duncan Laurie 70c86d9b26 acpi_device: Add support for writing ACPI SPI descriptors
Add required definitions to describe an ACPI SPI bus and a method to
write the SpiSerialBus() descriptor to the SSDT.

This will be used by device drivers to describe their SPI resources to
the OS.  SPI devices are not currently enumerated in the devicetree but
can be enumerated by device drivers directly.

generic.c:
  void acpi_fill_ssdt_generator(struct device *dev) {
    struct acpi_spi spi = {
      .device_select = dev->path->generic.device.id,
      .device_select_polarity = SPI_POLARITY_LOW,
      .spi_wire_mode = SPI_4_WIRE_MODE,
      .speed = 1000 * 1000; /* 1 mHz */
      .data_bit_length = 8,
      .clock_phase = SPI_CLOCK_PHASE_FIRST,
      .clock_polarity = SPI_POLARITY_LOW,
      .resource = acpi_device_path(dev->bus->dev)
    };
    ...
    acpi_device_write_spi(&spi);
    ...
  }

devicetree.cb:
  device pci 1e.2 on
    chip drivers/spi/generic
      device generic 0 on end
    end
  end

SSDT.dsl:
  SpiSerialBus (0, PolarityLow, FourWireMode, 8, ControllerInitiated,
                1000000, ClockPolarityLow, ClockPhaseFirst,
                "\\_SB.PCI0.SPI0", 0, ResourceConsumer)

Change-Id: I0ef83dc111ac6c19d68872ab64e1e5e3a7756cae
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14936
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-28 03:48:06 +02:00
Duncan Laurie 1010b4aeac acpi_device: Add support for writing ACPI I2C descriptors
Add required definitions to describe an ACPI I2C bus and a method to
write the I2cSerialBus() descriptor to the SSDT.

This will be used by device drivers to describe their I2C resources to
the OS.  The devicetree i2c device can supply the address and 7 or 10
bit mode as well as indicate the GPIO controller device, and the bus
speed can be fixed or configured by the driver.

chip.h:
  struct drivers_i2c_generic_config {
    enum i2c_speed bus_speed;
  };

generic.c:
  void acpi_fill_ssdt_generator(struct device *dev) {
    struct drivers_i2c_generic_config *config = dev->chip_info;
    struct acpi_i2c i2c = {
      .address = dev->path->i2c.device,
      .mode_10bit = dev->path.i2c.mode_10bit,
      .speed = config->bus_speed ? : I2C_SPEED_FAST,
      .resource = acpi_device_path(dev->bus->dev)
    };
    ...
    acpi_device_write_i2c(&i2c);
    ...
  }

devicetree.cb:
  device pci 15.0 on
    chip drivers/i2c/generic
      device i2c 10.0 on end
    end
  end

SSDT.dsl:
  I2cSerialBus (0x10, ControllerInitiated, 400000, AddressingMode7Bit,
                "\\_SB.PCI0.I2C0", 0, ResourceConsumer)

Change-Id: I598401ac81a92c72f19da0271af1e218580a6c49
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14935
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-28 03:47:09 +02:00
Duncan Laurie cfb6ea7e65 acpi_device: Add support for writing ACPI GPIO descriptors
Add definitions to describe GPIOs in generated ACPI objects and a
method to write a GpioIo() or GpioInt() descriptor to the SSDT.

ACPI GPIOs have many possible configuration options and a structure
is created to describe it accurately in ACPI terms.  There are many
shared descriptor fields between GpioIo() and GpioInt() so the same
function can write both types.

GpioInt shares many properties with ACPI Interrupts and the same types
are re-used here where possible.  One addition is that GpioInt can be
configured to trigger on both low and high edge transitions.

One descriptor can describe multiple GPIO pins (limited to 8 in this
implementation) that all share configuration and controller and are
used by the same device scope.

Accurately referring to the GPIO controller that this pin is connected
to requires the SoC/board to implement a function handler for
acpi_gpio_path(), or for the caller to provide this directly as a
string in the acpi_gpio->reference variable.

This will get used by device drivers to describe their resources in
the SSDT.  Here is a sample for a Maxim 98357A I2S codec which has a
GPIO for power and channel selection called "sdmode".

chip.h:
  struct drivers_generic_max98357a_config {
    struct acpi_gpio sdmode_gpio;
  };

max98357a.c:
  void acpi_fill_ssdt_generator(struct device *dev) {
    struct drivers_generic_max98357a_config *config = dev->chip_info;
    ...
    acpi_device_write_gpio(&config->sdmode_gpio);
    ...
  }

devicetree.cb:
  device pci 1f.3 on
    chip drivers/generic/max98357a
      register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_C5)"
      device generic 0 on end
    end
  end

SSDT.dsl:
  GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
          "\\_SB.PCI0.GPIO", 0, ResourceConsumer, ,) { 53 }

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ibf5bab9c4bf6f21252373fb013e78f872550b167
Reviewed-on: https://review.coreboot.org/14934
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-28 03:46:29 +02:00
Duncan Laurie 6b7c1f605c acpi_device: Add support for writing ACPI Interrupt descriptors
Add definitions for ACPI device extended interrupts and a method to
write an Interrupt() descriptor to the SSDT output stream.

Interrupts are often tied together with other resources and some
configuration items are shared (though not always compatibly) with
other constructs like GPIOs and GPEs.

These will get used by device drivers to write _CRS sections for
devices into the SSDT.  One usage is to include a "struct acpi_irq"
inside a config struct for a device so it can be initialized based
on settings in devicetree.

Example usage:

chip.h:
  struct drivers_i2c_generic_config {
    struct acpi_irq irq;
  };

generic.c:
  void acpi_fill_ssdt_generator(struct device *dev) {
    struct drivers_i2c_generic_config *config = dev->chip_info;
    ...
    acpi_device_write_interrupt(&config->irq);
    ...
  }

devicetree.cb:
  device pci 15.0 on
    chip drivers/i2c/generic
      register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)"
      device i2c 10 on end
    end
  end

SSDT.dsl:
  Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive,,,) { 31 }

Change-Id: I3b64170cc2ebac178e7a17df479eda7670a42703
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14933
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-28 03:40:35 +02:00
Aaron Durbin b3f5418ec1 soc/intel/apollolake: provide SMM dependency requirements
Depending on which options are selected there needs to be certain
functions supplied. However, the spi, mmap_boot, and tsc_freq modules
were not included in the SMM builds. Fix the omission.

Change-Id: I25ab42886cfd46770ce0f4beee65f2f4d15649f3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14977
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-27 19:56:01 +02:00
Aaron Durbin 07dd474d65 mainboard/google/reef: increase BIOS region size
An updated descriptor expands the BIOS region while descreasing
the 'device expansion region' utilized by the CSE. Update the
end region marker to reflect this new size as well as the
chromeos.fmd file which needs to be adjusted for logical boot
parition 2 requirement which resides halfway through the BIOS
region. The GBB was moved and shunk to accommodate the change.

Change-Id: I7baa5282d7c608af648b5773c4dfa123060a6e45
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14974
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-05-27 19:55:30 +02:00
Furquan Shaikh 2b56ba5a4f google/reef: Sync chromeos.fmd with fmap.dts and fix offsets
CQ-DEPEND=CL:347460
BUG=chrome-os-partner:53689
BRANCH=None
TEST="emerge-reef chromeos-bootimage" completes without error

Change-Id: Ic954e29628423937604772a8d2d0414954e6ba3e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/347441
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/14975
Tested-by: build bot (Jenkins)
2016-05-27 19:54:43 +02:00
Aaron Durbin 7a3edb6f27 mainboard/google/reef: support verstage
The chromeos.c suport needs to be linked into verstage so it will
link.

Change-Id: If85e232a3721443edfbbd278b32f72302f13f3a8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14973
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-27 19:54:06 +02:00
Aaron Durbin bef75e7dd9 soc/intel/apollolake: add support for verstage
There previously was no support for building verstage on apollolake.
Add that suport by linking in the appropriate modules as well as
providing vboot_platform_is_resuming(). The link address for verstage
is the same as FSP-M because they would never be in CAR along side
each other. Additionally, program the ACPI I/O BAR and enable decoding
so sleep state can be determined for early firmware verification.

Change-Id: I1a0baab342ac55fd82dbed476abe0063787e3491
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14972
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-05-27 19:53:34 +02:00
Aaron Durbin 10221a0e57 arch/x86: provide verstage support for CONFIG_C_ENVIRONMENT_BOOTBLOCK
When CONFIG_C_ENVIRONMENT_BOOTBLOCK is employed there's no need for
a chipset specific verstage entry point because cache-as-ram has
already been initialized. Therefore, provide a default entry point
for verstage in that environment.

Change-Id: Idd8f45bd58d3e5b251d1e38cca7ae794b8b77a28
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14971
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-05-27 19:53:16 +02:00
Jagadish Krishnamoorthy a9ac2d9b91 soc/intel/apollolake: Provide No Connect macro for unused Pad
Change-Id: Iba506054a3d631c8e538d44e1ca6877dd02c2ca9
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/14956
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-26 23:54:25 +02:00
Andrey Petrov 842dfe8d63 MAINTAINERS: Add myself for Apollolake SoC, FSP2.0, and Amenia mb
Change-Id: I9931263f0f51d6c726bd7c72042fae1155affb6e
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14963
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-26 23:52:57 +02:00
Jagadish Krishnamoorthy b6b233a6e5 soc/intel/apollolake: enable RTC
BUG=none
TEST=Boot to OS and verfiy if rtc0 device is created
under /sys/class/rtc/

Change-Id: Idec569255859816fda467bb42a215c00f7c0e16e
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/14883
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-26 23:52:25 +02:00
Furquan Shaikh 1ac194e14a cbfstool: Move cbfs_file_get_header to fit.c
Since fit.c is the only caller of this function move it out of common.c
and into fit.c.

Change-Id: I64cc31a6d89ee425c5b07745ea5ca9437e2f3fcf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14949
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-26 23:51:08 +02:00
Alexandru Gagniuc c4ea8f7d3f drivers/intel/fsp2_0: Send post codes around calls to the blobs
By design, FSP will send POST codes to port 80. In this case we have
both coreboot and FSP pushing post codes, which may make debugging
harder. In order to get a clear picture of where FSP execution begins
and ends, send post codes before and after any call to the FSP blobs.

Note that sending a post code both before and after is mostly useful
on chromeec enabled boards, where the EC console will provide a
historic list of post codes.

Change-Id: Icfd22b4f6d9e91b01138f97efd711d9204028eb1
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14951
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-26 23:50:02 +02:00
zbao c16918ac11 splash: Put the suffix of splash file to CBFS name
The previous code harded the suffix of splash file as
"jpg". Actually, SeaBIOS supports both jpg and bmp.

Change-Id: I06c4b14aae7f75be3406652a94612b5f30ce91c2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/14932
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-26 23:48:02 +02:00
Alexandru Gagniuc 944655dada soc/apollolake: Use simpler macros for the northbridge PCI device
The NB_DEV_ROOT macro, is almost unreadable, as it depends on other
stringified macros, and acts differently depending on the coreboot
stage. For ramstage, it also hides a function call.
Rewrite the macro in terms of more basic and readable macros.

Change-Id: I9b7071d67c8d58926e9b01fadaa239db1120448c
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14890
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-26 23:46:59 +02:00
Alexandru Gagniuc bbac5ace53 soc/apollolake/memmap: Switch to SIMPLE_DEVICE API
memmap.c functionality is designed to be used in more than ramstage.
Therefore, it cannot use ramstage-specific APIs. In this case, the
SIMPLE_DEVICE API offers a more consistent behavior across stages.

Change-Id: Ic381fe1eb773fb0a5fb5887eb67d2228d2f0817d
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14953
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-26 23:46:25 +02:00
Abhay Kumar 1285598a99 mainboard/intel/amenia: Configure DDI0, DDI1 HPD GPIO lines.
1. Configure GPIO_199 and GPIO_200 as NF2 to work as HPD.
2. Make 20k Pullup and remove duplicate code.

Change-Id: I8c78d867b03d5f2a6f02165c20777ae25e352ce7
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/14899
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-26 17:26:23 +02:00