This reverts commit 68d0e4a5a1.
Special handling of MPFR is no longer needed with the latest
MPFR release.
Change-Id: I96d9ea92cfb74eed6af2ba62254f0678081e2b4f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12833
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The current MPFR version contains a stale config.guess file
that requires special handling on ppc64el systems. Bump
the MPFR version to the latest release.
Change-Id: I5e86c732c09f8a6a43f9812452124d64d337ea3f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12832
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested on C3/EPIA board and Linux x86
Change-Id: I8df551f4b385ee8702af78df00169bdc8e180925
Signed-off-by: Andrey Korolyov <andrey@xdel.ru>
Reviewed-on: https://review.coreboot.org/12851
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The cbfs master header's offset and romsize fields are absolute values
within the boot media proper. Therefore, when adding a master header
provide the offset of the CBFS region one is operating on as well as
the absolute end offset (romsize) to match expectations.
Built with and without CBFS_SIZE != ROM_SIZE on x86 and ARM device. Manually
inspected the master headers within the images to confirm proper caclulations.
Change-Id: Id0623fd713ee7a481ce3326f4770c81beda20f64
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12825
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
For the purposes of maintaining integrity of a CBFS allow one to
hash a CBFS over a given region. The hash consists of all file
metadata and non-empty file data. The resulting digest is saved
to the requested destination region.
BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Integrated with glados chrome os build. vboot verification
works using the same code to generate the hash in the tooling
as well as at runtime on the board in question.
Change-Id: Ib0d6bf668ffd6618f5f73e1217bdef404074dbfc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12790
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Adding new files overwrote the header with the empty file (ie 0xff),
so carve out some space.
BUG=chromium:445938
BRANCH=none
TEST=none
Change-Id: I91c292df381c2bac41c6cb9dda74dae99defd81d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/12789
Tested-by: build bot (Jenkins)
These need to go together, so the commit became a bit larger than
typial.
- Add an option -R for the copy source fmap region.
Use: cbfstool copy -r target-region -R source-region.
- Don't generate a CBFS master header because for fmap regions, we
assume that the region starts with a file header.
Use cbfstool add-master-header to add it afterwards, if necessary.
- Don't copy files of type "cbfs master header" (which are what cbfstool
add-master-header creates)
- Leave room for the master header pointer
- Remove -D command line option as it's no longer used.
BUG=chromium:445938
BRANCH=none
TEST=Manual test on image and integration test w/ bundle_firmware
changes.
CQ-DEPEND=CL:313770,CL:313771
Change-Id: I2a11cda42caee96aa763f162b5f3bc11bb7992f9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12788
Tested-by: build bot (Jenkins)
This allows adding support for FMAP based cbfstool copy more easily.
BUG=chromium:445938
Change-Id: I72e7bc4da7d27853e324400f76f86136e3d8726e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/12787
Tested-by: build bot (Jenkins)
Let toolchain.inc error out when the architecture or tool is missing.
Change-Id: I39a51e5a2c778d6bbc50354807e5e2b717fa9e52
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12682
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The config.guess file included with MPFR is completely obsolete,
leading to build failures on ppc64el due to the system architecture
not being detected. Regenerate the files from the host system via
automake before attempting to build MPFR.
Change-Id: I00fc16003906e373d112c25978197ac907adccfd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12816
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The previous official GMP release (6.0.0) contains a bug that
prevents compilation on ppc64el systems. Increase version
to the latest version (6.1.0).
Bug details:
gcc build on ppc64el fails with:
(.text+0x4c): undefined reference to `BMOD_1_TO_MOD_1_THRESHOLD'
While I don't have an exact commit hash due to Hg use upstream,
a missing BMOD_1_TO_MOD_1_THRESHOLD define on ppc64el was quietly
fixed in Hg before the 6.1.0 release.
Change-Id: I1c05a1c194141db5f8522148c2e20e7558d34714
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12811
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
When coreboot is pulled in as a submodule, the .git "folder" is a file,
not a folder. Use the '-e' test instead of '-d' to allow for that.
Change-Id: I0dd8866b0016f7ba099cdaf4d7db442ff22612b5
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12819
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Using origin/master as the git revision breaks reproducibility, giving
different values depending on when the code was pulled from the
repo at coreboot.org. By using the current revision instead, we get
identical builds.
Change-Id: If4be6e048d6c8e417b8c074199745900ccd82b49
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12807
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
clang version now returns:
coreboot toolchain v1.33 November 25th, 2015 clang version 3.6.1
(tags/RELEASE_361/final) (based on LLVM 3.6.1)
Change-Id: I948d7f4d06c244987342cfc7d5c7e728cbed93bd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12777
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Quoting variables prevents word splitting and glob expansion, and
prevents the script from breaking when input contains spaces, line
feeds, glob characters and such.
See shellcheck warning SC2086.
Change-Id: I7256d2fc2a22bce7723950a534fef6d57cbd097f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12761
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This allows users who build the rom from the board-status repo to
verify that their rom matches the original.
Change-Id: I4e8564e389495909219f92ccdafb8e9568f8f0d0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12760
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Print what the script is doing so when it asks for the ssh password
several times in a row, it's obvious that it's actually doing different
things, not that the password failed.
- Don't print the output from cbfstool - it's not useful.
Change-Id: I785283475e14f242117682800c26db6b4f9f1e2c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12759
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If the payload_config and payload_version files are in coreboot.rom,
extract and save them.
Change-Id: I36b17ed189f94e2d4e873b0e219e5a9a2abe77a1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12758
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The old serial port read method lost characters from the boot log. This
method works better for me.
- Put get_serial_bootlog arguments into variable names for clarity.
- Fully configure the serial port with stty: disable parity and flow control.
- Change serial port read from reading with 'cat' to reading with 'read'.
- Update help to show current default speed from the variable.
tested under dash, bash, and zsh on several platfoms.
Change-Id: I91ae63a3c226e61019dbdf69c405c3f20ba7db54
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12757
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the coreboot toolchain version to iasl's version output.
% ./xgcc/bin/iasl -v
Intel ACPI Component Architecture
ASL+ Optimizing Compiler version 20150619-64
Copyright (c) 2000 - 2015 Intel Corporation
coreboot toolchain v1.33 November 25th, 2015
This won't actually be checked until the next version of
iasl so that we don't have to rebuild again for no reason.
The buildgcc version was intentionally not incremented for
this minor change.
Change-Id: I03a1a777fdb84e34bfceb7b1eb43fffbc1f3a2fc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12688
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The constant for ppc64 is 'hotstuff'. For many reasons.
Note that line 2894 of elf.h is not indented. This is because in the
original the line begins with a space. Checkpatch rejects that.
Checkpatch also rejects changing the space to a tab because that makes
it more than 80 chars. I rejected breaking the line because it makes it
even less readable. All the changes forced by checkpatch make the code
less readable.
Herman Hollerith would be proud.
Change-Id: I21f049fe8c655a30f17dff694b8f42789ad9efb7
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/12711
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
We still add a master header for compatibility purposes, and the default
layouts don't cover anything non-coreboot (eg. IFD regions) yet.
The default layouts can be overridden by specifying an fmd file, from
which the fmap is generated.
Future work:
- map IFD regions to fmap regions
- non-x86: build minimalistic trampolines that jump into the first cbfs
file, so the bootblock can be part of CBFS instead of reserving a
whole 64K for it.
- teach coreboot's cbfs code to work without the master header
- teach coreboot's cbfs code to work on different fmap regions
Change-Id: Id1085dcd5107cf0e02e8dc1e77dc0dd9497a819c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/11692
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The former interpretation sprung from the x86 way of doing things
(assuming top-alignment to 4GB). Extend the mechanism to work with CBFS
regions residing elsewhere.
It's compatible with x86 because the default region there resides at the
old location, so things fall in place. It also makes more complex
layouts and non-x86 layouts work with negative base addresses.
Change-Id: Ibcde973d85bad5d1195d657559f527695478f46c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12683
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
I didn't go back through the development guide for this.
But based on test, if the empty entry is filled as 0xFFFFFFFF,
instead of 0, the USB3 port can not be used.
Leave the entries of PSP and PSP2 as 0xFFFFFFFF to be compliant
with the case before the amdfwtool is used.
Change-Id: Icd5f9891e541279dbd551bbceaf091488d22bfef
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/12665
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Until there's a reason to, don't print a warning about the missing
power8 compiler.
Change-Id: I47c60e0a16892f0fa228e1439e0424926bca00a4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12634
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
The help text had gotten kind of sloppy. There was a missing newline
in the add-stage command, some of the lines were too long, etc.
Change-Id: If7bdc519ae062fb4ac6fc67e6b55af1e80eabe33
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12646
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
- Including the help targets in the list of NOCOMPILE targets means they
can run even if the toolchain is mucked up. Since they contain info on
building the toolchin, this is useful.
- Separate the three current parts of the help target into individual
components: help_coreboot, help_toolchain, and help_kconfig. This is
mostly for the help_toolchin target which will be printed out by
toolchain.inc.
Change-Id: I365d95fd63e22bddd122fb1fede6f04270e03d63
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12542
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
power8 is set up by ibm as a powerpc subset, so we follow
that rule here: we call it a powerpc but require -mcpu=power8
Change-Id: Ib5212be22db9584b0dc0eeed5c06ec1924347067
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/12624
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
ERROR: code indent should use tabs where possible
+^I trampoline_len);$
Change-Id: If46f977e2e07d73e6cfd3038912a172236a7e571
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12620
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
It's not needed, so we can remove some extra file mangling, too.
Change-Id: I80d707708e70c07a29653258b4cb6e9cd88d3de3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12508
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add the code necessary to create the linux trampoline blob.
Don't enforce this for the in-coreboot build or use objcopy
to produce linux_trampoline.o as it is a bit trickier to get
all the details right than I had hoped:
- you have to know the elf architecture of the host machine
- you might have to have more tools (xxd, perl, etc) installed
Change-Id: I9b7877c58d90f9fb21d16e0061a31e19fffa2470
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12505
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The existing code used a stale pointer from a previously unmapped
region of memory when parsing the coreboot tables. Use the correct
pointer from the currently mapped memory region when parsing.
Change-Id: Id9a1c70655fe25bc079e5bee55f15adf674694f8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12619
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The previous code would miss the first of two IS_ENABLED(CONFIG_symbol)
sequences on a line. This patch saves the rest of the line and loops
to check any other entries on the same line of text.
Change-Id: If4e66d5b393cc5703a502887e18f0ac11adff012
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12562
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Combine the file and line number into a combination that editors
understand when opening files. This makes it easier to edit the
errors.
Change-Id: Id2fae6a0a2ca8d726b95e252d80ac918f4edbe23
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12561
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Create subroutines for printing warnings and errors
- Change all the existing warning and error routines to use subroutines
- Add new command line options to suppress errors and to print notes
Change-Id: I04893faffca21c5bb7b51be920cca4620dc283c3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12555
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
By adding the version number of tools, we can help people keep up to
date with their tool versions. This will be used now to determine
whether the IASL version being used is the version supported by
coreboot.
Change-Id: I24a68b01c819871f90403869570125e71b96bd70
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12545
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Mingw doesn't have that this function.
Change-Id: I640ea61ff24fba812e3f10771dd7e468dcfc63dd
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/11724
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This makes the make process look like the one inside
of coreboot's build system.
Change-Id: I48be2df39cad47644e16ce583b27c33a1da81fc3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12509
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
PSP2 is for Combo BIOS, which is the idea that one image supports 2
kinds of APU.
The PSP2 feature is for the future, not for current products.
The newest document about PSP2 is not available. I made it from the
draft code I made when I was in AMD.
Change-Id: I65328db197c02ee67f3e99faf4ab8acabd339657
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/12474
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Currently running 'make help' just gives help for the kconfig targets.
This adds help for common coreboot and toolchain targets. It stops
printing some of the less common kconfig targets, but still leaves
them in the makefile as documentation.
Change-Id: I2a00fcbc06f05dc4029a91f3dff830c19e4d1329
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12458
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
mma_setup_test.sh is used to set MMA test name and MMA test config
name. After executing this script user needs to reboot the system and
FSP/coreboot would execute the selected MMA test. FSP and coreboot needs
to be built with MMA support.
mma_get_result.sh will get the raw MMA results from cbtable and save it
to bin file.
BRANCH=none
BUG=chrome-os-partner:43731
TEST=Build and Boot kunimitsu (FAB3).
CQ-DEPEND=CL:299476,CL:299475,CL:299474,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479
Change-Id: Ie330151535809676167f0b22c504a71975841414
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 35469218fe53c1ac211f55bd26a206a05a827453
Original-Change-Id: I7d20aca63982e13edc41be2726f3cc7e41d95bae
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/299473
Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: http://review.coreboot.org/12483
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Changed following things,
(1) cbmem -l would give both ID and Name for coreboot table along with
START and LENGTH of each entry
e.g.
localhost ~ # cbmem -l
CBMEM table of contents:
NAME ID START LENGTH
<.....>
3. TIME STAMP 54494d45 77ddd000 000002e0
4. MRC DATA 4d524344 77ddb000 00001880
5. ROMSTG STCK 90357ac4 77dd6000 00005000
6. VBOOT WORK 78007343 77dd2000 00004000
7. VBOOT 780074f0 77dd1000 00000c3c
8. RAMSTAGE 9a357a9e 77d13000 000be000
9. REFCODE 04efc0de 77c01000 00112000
10. ACPI GNVS 474e5653 77c00000 00001000
11. SMM BACKUP 07e9acee 77bf0000 00010000
<..etc..>
(2) With this patch, new command line arg "rawdump" or "-r" will be
added to cbmem
user can grab the ID with "cbmem -l" and execute "cbmem -r <ID>" to get
raw dump of cbtable for the <ID> in interest.
This change is needed to get MMA results data from cbtable. Coreboot
stores the MMA results in cbmem. Separate post processing scripts uses
cbmem utility to get the these data.
This feature in the cbmem tool can also help debugging some issues where
some specific ID of cbtable needs examination.
BRANCH=none
BUG=chrome-os-partner:43731
TEST=Build and Boot kunimitsu (FAB3). Cbmem -r and -l works as described.
Not tested on Glados
CQ-DEPEND=CL:299476,CL:299475,CL:299473,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479
Change-Id: I70ba148113b4e918646b99997a9074300a9c7876
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f60c79d845d4d4afca480b6884c564a0d5e5caf8
Original-Change-Id: I1dde50856f0aa8d4cdd3ecf013bd58d37d76eb72
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Signed-off-by: Icarus Sparry <icarus.w.sparry@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/299474
Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: http://review.coreboot.org/12482
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Building cbmem with ASan
$ CC=gcc-5 CFLAGS="-O1 -g -fsanitize=address -fno-omit-frame-pointer" LDFLAGS="-fsanitize=address" make
it sometimes finds a heap-buffer-overflow, while dumping the CBMEM
console.
$ sudo ./cbmem -c
=================================================================
==11208==ERROR: AddressSanitizer: heap-buffer-overflow on address 0xb5d5782b at pc 0x0804a4d7 bp 0xbfe23bc8 sp 0xbfe23bbc
WRITE of size 1 at 0xb5d5782b thread T0
#0 0x804a4d6 in dump_console /home/joey/src/coreboot/util/cbmem/cbmem.c:553
#1 0x804a4d6 in main /home/joey/src/coreboot/util/cbmem/cbmem.c:1134
#2 0xb70a3a62 in __libc_start_main (/lib/i386-linux-gnu/i686/cmov/libc.so.6+0x19a62)
#3 0x8048cf0 (/home/joey/src/coreboot/util/cbmem/cbmem+0x8048cf0)
0xb5d5782b is located 50 bytes to the right of 131065-byte region [0xb5d37800,0xb5d577f9)
allocated by thread T0 here:
#0 0xb72c64ce in __interceptor_malloc (/usr/lib/i386-linux-gnu/libasan.so.2+0x924ce)
#1 0x804a407 in dump_console /home/joey/src/coreboot/util/cbmem/cbmem.c:542
#2 0x804a407 in main /home/joey/src/coreboot/util/cbmem/cbmem.c:1134
#3 0xb70a3a62 in __libc_start_main (/lib/i386-linux-gnu/i686/cmov/libc.so.6+0x19a62)
SUMMARY: AddressSanitizer: heap-buffer-overflow /home/joey/src/coreboot/util/cbmem/cbmem.c:553 dump_console
Shadow bytes around the buggy address:
0x36baaeb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x36baaec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x36baaed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x36baaee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x36baaef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
=>0x36baaf00: fa fa fa fa fa[fa]fa fa fa fa fa fa fa fa fa fa
0x36baaf10: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
0x36baaf20: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
0x36baaf30: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
0x36baaf40: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
0x36baaf50: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
Shadow byte legend (one shadow byte represents 8 application bytes):
Addressable: 00
Partially addressable: 01 02 03 04 05 06 07
Heap left redzone: fa
Heap right redzone: fb
Freed heap region: fd
Stack left redzone: f1
Stack mid redzone: f2
Stack right redzone: f3
Stack partial redzone: f4
Stack after return: f5
Stack use after scope: f8
Global redzone: f9
Global init order: f6
Poisoned by user: f7
Container overflow: fc
Array cookie: ac
Intra object redzone: bb
ASan internal: fe
==11208==ABORTING
Fix up commit 06b13a37 (cbmem: Terminate the cbmem console at the cursor
position.) by reverting setting the cursor to 0.
Change-Id: Id614a8e0f1a202671dd091f825d826a17176bfcc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10572
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Andrey Korolyov