Commit Graph

3834 Commits

Author SHA1 Message Date
Furquan Shaikh c42cf911ad util/cbfstool: Allow use of non-ASCII longopt
CB:29744 ("util/cbfstool: Add optional argument ibb") added support
for non-ASCII characters for long_options. However, there is a check
later on which errors out since this character is not one of the
commands[i].optstring.

This change adds a function valid_opt() which does the following
things:
1. Checks if the returned optchar is among the list of optstring
supported by the command.
2. Checks if the returned optchar is a valid non-ASCII
option. Currently, we do not maintain a list of non-ASCII options
supported by each command. So, this function returns true if the
optchar returned by getopt_long falls within the allowed range.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I27a4f9af9850e4c892573202904fa9e5fbb64df6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-20 06:08:29 +00:00
Iru Cai 56360d4f7b autoport: use GMA_STATIC_DISPLAYS
Change-Id: Ie988b2caeb2cdc07a3d6466b7ae3501df469ef41
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-16 10:15:21 +00:00
Iru Cai b95a1a4ea0 autoport: Support bigger ACPI tables
DSDT can be bigger than 0x10000 bytes, so increase the space up to 1MB
for an ACPI table and support lines in acpidump.log with address
higher than 0x10000.

Change-Id: Iaadcfd0964c1c516e9e39d6cbfe41ec9a8c45e9d
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31759
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-16 10:15:07 +00:00
Felix Held a6b887e017 src/Kconfig: enable USE_BLOBS by default
To provide sane defaults for most of the user base, this patch switches
on the USE_BLOBS option by default. Since it only changes the default,
this behaviour can still be easily disabled.

With this abuild doesn't have to select USE_BLOBS any more, so what
abuild tests becomes the coreboot default again.

Change-Id: Ia0632b9ae7a1f212a8640b3faec2695d17d238c5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14 10:03:55 +00:00
Rajat Jain 999001144f util/lint: Accept "GPL-2.0-only WITH Linux-syscall-note" licenses
The Linux kernel UAPI header files are licensed under
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */

Allows files with this license to be included in coreboot.
For more details about this particular license:

https://www.kernel.org/doc/html/v4.17/process/license-rules.html
https://spdx.org/licenses/Linux-syscall-note.html

Change-Id: I4f0f8d36c637a66a6999a18321fdbc4c42d5751e
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-13 19:54:19 +00:00
Elyes HAOUAS 7eed98ac88 util/nvramtool: Remove 2nd initialization
'result' is already defined as 'unsigned long long result = 0;' so no
need to re-write 'result = 0;'.

Change-Id: Ie897453fb5e7b09af755ce8d61ee8e80943ffc1c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-10 11:56:13 +00:00
Nico Huber 04da5d72d9 fsp2_0: Clean up around `config FSP_USE_REPO`
We can make our lifes much easier by removing its dependency on
`ADD_FSP_BINARIES`. Instead, we imply the latter if the repository
is to be used. We can also hide a lot of unnecessary prompts in
this case.

Also, remove default overrides and selects for the two that are
now unnecessary.

Change-Id: I8538f2e966adc9da0fbea2250c954d86e42dfeb3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39882
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-05 23:26:04 +00:00
Aaron Durbin d47afe90ef util/sconfig: emit NULL sibling fields
It's helpful to see the sibling field, even when it's NULL, when
debugging the static.c output from a devictree.cb file. Ensure the
NULL fields are emitted for fullness.

Change-Id: Ib6d5b8164769a6512e762d5a525c7df1f429c866
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-30 08:37:56 +00:00
Rob Barnes 18fd26cb08 amdfwtool: Allow for up to 16 APCB entries
Increase the number of allowed APCB entries in amdfwtool.

BUG=b:150455865
TEST=Boot Trembyle
BRANCH=None

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ibdd2f2b9766735bc9aba98b5216e589b6cace238
Reviewed-on: https://chromium-review.googlesource.com/2084944
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39861
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-27 22:52:48 +00:00
Paul Menzel 5e20c1cbc8 util/board-status: Reject logs from dirty images
Currently, there are a lot of uploads in the board status repository,
where the logs say, that the coreboot image or payload were built from a
dirty source tree. Add a check to reject such uploads.

Change-Id: I920e26a10f74e1f3b9b4e5f8c9284c59692a519b
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-25 20:03:03 +00:00
Nico Huber d07ac8ee13 drivers/intel/gma: Ditch `link_frequency_270_mhz` setting
The `link_frequency_270_mhz` setting was originally used by the native
graphics init code for Sandy/Ivy Bridge, which is long gone.

The value of this information (which board had it set) is questionable.
The only board that had an LVDS panel and set it to 0 was the ThinkPad
L520, where native graphics init was never reported to work. Also, the
native graphics init only used it for calculations, but never confi-
gured the hardware to use a specific frequency. A look into the docu-
mentation also doesn't reveal any straps that could be used to confi-
gure it.

Change-Id: Ieceaa13e4529096a8ba9036479fd84969faebd14
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39763
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-24 20:36:36 +00:00
Michael Niewöhner cc85ce0aa0 util/inteltool: add inteltool path to include path
Add the inteltool path to the include path to be able to avoid ugly
include hacks like `#include "../inteltool.h"`.

Change-Id: Id363fa20fe3b52248a224ca14b2626a8e3ce44a2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39744
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-24 16:33:59 +00:00
Marcello Sylvester Bauer e9aef1fe45 Doc/security/vboot: Add a script generated device list
Add a script generated list of vboot enabled devices to the
documentation. Add a entry to the release checklist.

Change-Id: Ibb57d26c5f0cb8efd27ca9a97fd762c25b566f93
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-23 09:23:11 +00:00
Yu-Ping Wu 0beddb5e23 cbfstool: Build vboot library
Currently cbfstool cherry-picks a few files from vboot and hopes these
files will work standalone without any dependencies. This is pretty
brittle (for example, CL:2084062 will break it), and could be improved
by building the whole vboot library and then linking against it.
Therefore, this patch creates a new target $(VBOOT_HOSTLIB) and includes
it as a dependency for cbfstool and ifittool.

To prevent building the vboot lib twice (one for cbfstool and the other
for futility) when building coreboot tools together, add the variable
'VBOOT_BUILD' in Makefile to define a shared build path among different
tools so that vboot files don't need to be recompiled.

Also ignore *.o.d and *.a for vboot library.

BRANCH=none
BUG=none
TEST=make -C util/cbfstool
TEST=make -C util/futility
TEST=Run 'make tools' and make sure common files such as 2sha1.c are
     compiled only once
TEST=emerge-nami coreboot-utils

Change-Id: Ifc826896d895f53d69ea559a88f75672c2ec3146
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-23 08:34:23 +00:00
Michael Niewöhner 10d522133e util/inteltool: use read* macros instead of pointers
Switch to using read* macros instead of pointers.

Change-Id: I1fe54b496a5998597b79cdd7108f3a4075744a78
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-21 22:12:10 +00:00
Michael Niewöhner 8ca1ada083 util/inteltool: powermgt: add code for dumping config registers
This adds the code required to dump config registers.

Change-Id: Ic78f847ba07240c112492229f9a23f9a88275ad9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-20 21:05:29 +00:00
Patrick Georgi 59e6f3c6e3 util/scripts/gerrit-rebase: Fix shell invocation
The single apostrophe confuses the shell that's calling the command.

Change-Id: I7d3183e9a612de0121b2d208c06a45645b8d67f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-20 11:06:12 +00:00
Angel Pons 3d5d6e8dc7 util/autoport: Emit SPDX license headers
Change-Id: I8896b6c92c3126cc611e47b39d596108b90c6bf2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-20 09:36:12 +00:00
Nico Huber 260ba6b25e util/xcompile: Split $CFLAGS_GCC
Split common flags that are not specific to the C language out of
$CFLAGS_GCC into $FLAGS_GCC. This way, we can test for C specific
flags, too, without adding them to $ADAFLAGS_*. Currently this is
done for `-Wno-address-of-packed-member` which only applies to C.

Change-Id: Ib793c62656efb07b6e5b3385f1ed1c96a40efd1d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39633
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20 09:33:35 +00:00
Rob Barnes 5baadba532 util/bincfg: Add DDR4 SPD spec
Additionally provide a simple script for decoding spd hex files using bincfg.

BUG=b:148561711
TEST=Decoded spd files in zork
BRANCH=None

Change-Id: Ic62868d59e075fd6816d7be55cc935e3e3f82499
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/2067697
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-03-19 10:31:08 +00:00
Angel Pons 1cd7d3e664 util/lint/spelling.txt: Disable `afe`
Uppercase `AFE` is an acronym for `Analog Front-End`. As it is a valid
spelling, comment out its entry to prevent false positives.

Change-Id: Ib8612d970d33d4955c572838bda217cfdb49dfe6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18 21:39:42 +00:00
Angel Pons dc1c30ac17 util/lint/spelling.txt: Explain the commented-out entries
If they were removed instead, it would be too easy to end up adding them
back again. They are kept in a comment so that they can be tracked.

Also, explain why these two entries have been commented out.

Change-Id: I8225944b5e3d1e022af169dda33e0344d4c3bccd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18 21:38:35 +00:00
Michael Niewöhner b6b8575c0a util/inteltool: powermgt: make Sunrise Point dumping work
The existing Sunrise Point ids are assigned to the wrong implementation,
which would never work for these chipsets. Assign them to the right
dumping implementation, which works for both Sunrise Point PCH-H and
PCH-LP.

This also adds some missing device ids from doc#332691-003EN and
doc#334659-005.

Change-Id: Id102ef3809d675dc9a915d2cb3062e093487fa27
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18 18:09:56 +00:00
Angel Pons 223a30ce11 util/autoport: Correct formatting issues
There is no need to use hexadecimal values in azalia codec IDs, nor need
to print a redundant "LPC bridge PCI-LPC bridge" comment.

Change-Id: I6658051c7a3d5b65a86ccca8bab7834bf4628a16
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-18 16:45:38 +00:00
Michael Niewöhner a808d63cd1 util/inteltool: Makefile: add src/arch to includes.
Add src/arch to includes.

Change-Id: I157178a055a259e40c57f3915671d3b8966fbb96
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-18 16:32:40 +00:00
Eric Peers af505671a1 util/amdfwtool: Fix file open error msg
Print out the name of the file that failed to open.

BUG=none
TEST=rerun build-board.sh with missing files
BRANCH=none

Signed-off-by: Eric Peers <epeers@google.com>
Change-Id: Id8543f25ea827fc8764e0315434b834e65bfa7fb
Reviewed-on: https://chromium-review.googlesource.com/2090667
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-17 22:49:09 +00:00
Michael Niewöhner d3dab12244 util/inteltool: spi: add a bunch of missing chipsets to print_bioscntl
Add a bunch of missing chipsets to print_bioscntl.

Change-Id: I96c010a1d64dcf5296f78a6decd1a218aba4b04f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-17 01:00:32 +00:00
Michael Niewöhner 9952e72d06 util/inteltool: add code for dumping LPC registers
This adds the implementation for dumping LPC registers

Change-Id: I50ae4913933f7594f0d63ce3f752302ed5c461e2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39517
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17 00:25:04 +00:00
Michael Niewöhner fe8170f909 util/inteltool: ahci: add Sunrise Point config and SIR registers
This adds the Sunrise Point AHCI config and SIR registers from
doc#332691-003EN.

Change-Id: Id4a462d625194a6ccfdb88fb415d5eb278f2900a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39506
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 22:41:33 +00:00
Michael Niewöhner e6cff0d830 util/inteltool: ahci: add code for dumping config and SIR registers
This adds the code required to dump config and SIR registers.

Change-Id: I3726c52d415ff4dd6b19513b310f11254f7fbf92
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39560
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 22:41:07 +00:00
Michael Niewöhner 8676c268a0 util/inteltool: ahci: rework AHCI
Rework AHCI to align the code with the rest of inteltool.

Change-Id: I37116f8e269d0376e147dd6de7365c45ac90bda0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39504
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 22:38:31 +00:00
Matt DeVillier 3c78445ad9 inteltool: add support for CannonPoint-LP
Add support for CannonPoint-LP U Premium
(CoffeeLake-U and WhiskeyLake-U)

GPIO info taken from:
- Intel doc #337867-002
- coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs.h

Test: Read GPIOs from out-of-tree WhiskeyLake-U board

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I70f23eec71abb8d7c2a7a109c9e760bb31dee2ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39393
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 15:22:31 +00:00
Johanna Schander e32ded82f0 util/inteltool: Split GPIO community switch-case into its own function
So far printing the GPIO groups chose the community definition. As the
list of supported platforms grows the massive switch case gets repetetive
and hinders the readers view.
It also reduces the ability to reuse the code in a potential libinteltool.
To takle these issues the detection logic was split into its own function.

Change-Id: I215c1b7d6ec164b8afd9489ebd54b63d3df50cb9
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38631
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 15:21:58 +00:00
Johanna Schander 7da602ff47 util/inteltool: Move Denverton definitions into their own header
So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moved the Denverton definitions into its own header.

Change-Id: I6ce672c24059b9f3a4a984766184066f14df3013
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38630
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 15:20:41 +00:00
Johanna Schander aff7d1f864 util/inteltool: Move Lewisburg definitions into their own header
So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moves the Lewisburg definitions into its own header.

Change-Id: I7900f1d8b3ca022112874ac2fa7326d538166008
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38629
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 15:20:32 +00:00
Johanna Schander e98af86a2e util/inteltool: Move Sunrise Point (LP) definitions into their own header
So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moves the Sunrise Point and Sunrise Point LP definitions
into its own header.

Change-Id: I06efbee700f1525770365428fb85ef700ac53b80
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38628
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 15:20:24 +00:00
Johanna Schander f80c5d9133 util/inteltool: Move Apollo Lake definitions into their own header
So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moves the Apollo Lake definitions into its own header.

Change-Id: I44b21092f5495f758c1f2151a913c074dfc658f5
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38627
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 15:20:11 +00:00
Johanna Schander d5a65304c0 util/inteltool: Move Cannon Lake definitions into their own header
So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moves the Cannon Lake definitions into its own header.

Change-Id: I5991c3cebba0e05504940ae66fa7bb63bf280ab1
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38626
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 15:19:56 +00:00
Johanna Schander dca20cd77f util/inteltool: Move Ice Lake definitions into their own header
So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moves the Ice Lake definitions into its own header.

Change-Id: I5735f12480091a9b6c5e5c103a1ca7b7b1f3f997
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38625
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 15:19:42 +00:00
Patrick Rudolph 6b88f90f06 Revert "crossgcc: Upgrade GCC to 9.2.0"
Revert the upgrade as it breaks at least the devicetree parser on
aarch64, tested on qemu aarch64 target.

This reverts commit dfd3f21174.

Change-Id: I65607817188db21533014caa6d15be9a2004d498
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-16 14:45:32 +00:00
Martin Roth e7a5062997 util/crossgcc: Temporarily disable GDB build test on server
The latest debian builder image doesn't compile GDB correctly.  Disable
the build test until I can get it working again.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I7852a39ed40a7364d24d0bbf014fd25058491083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39575
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 14:45:20 +00:00
Michael Niewöhner 0d1366dedc util/inteltool: add 6th gen. mobile core u/y series
This adds the 6th gen. mobile core u/y series.

Change-Id: I7d802452353afe568e3880765dcd340f0437b392
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39568
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16 14:43:22 +00:00
Michael Niewöhner 099975debd util/inteltool: powermgt: rename variable for consistency
Rename size variable for consistency with the other subsystems.

Change-Id: I9407193ac9e34685362619cfd45384156e2385c3
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39507
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15 13:05:31 +00:00
Michael Niewöhner ee1739cd00 util/inteltool: powermgt: initialize register size variables
Initialize register size variables to prevent segfaults.

Change-Id: Ib89bf6f7c7582efdea1c54d1316ed8f33a87cfcc
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39513
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15 13:05:17 +00:00
Angel Pons 31b7ee4201 treewide: Replace uses of "Nehalem"
The code in coreboot is actually for the Arrandale processors, which
are a MCM (Multi-Chip Module) with two different dies:

- Hillel:   32nm Westmere dual-core CPU
- Ironlake: 45nm northbridge with integrated graphics

This has nothing to do with the older, single-die Nehalem processors.
Therefore, replace the references to Nehalem with the correct names.

Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15 13:04:39 +00:00
Angel Pons 95de2317c6 nb/intel/nehalem: Rename to ironlake
The code is for Arrandale CPUs, whose System Agent is Ironlake.

This change simply replaces `nehalem` with `ironlake` and `NEHALEM`
with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as
changing some of them would impact the resulting binary.

Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and packardbell/ms2290 does not change.

Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15 13:04:20 +00:00
Michael Niewöhner 2aff3005e0 util/inteltool: powermgt: drop dead code
Drop dummy entry.

Change-Id: I1257115bd73fe90c6435116c8705cb5c98d945e1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39559
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15 13:02:28 +00:00
Michael Niewöhner fdd5afde49 util/inteltool: gpio: drop dead code
Drop dummy entry.

Change-Id: Ic2184453c628c034e40ba877791fab4b7fe1d934
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39558
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15 13:02:07 +00:00
Paul Fagerburg 6e5693386b coreboot: add Volteer template files
Add template files for making a new barebones-copy of Volteer.

BUG=b:147483699
BRANCH=None
TEST=N/A

Change-Id: I8cc69b8ce7dbc6809de058019bdc466a060069e7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-03-14 23:41:14 +00:00
Bartek Pastudzki 69a88ddb5d util/scripts/ucode_h_to_bin.sh: Accept microcode in INC format
Intel supplies microcode (at least for MinnowBoard) in Intel Assembly
*.inc format rather than C header. This change allow to pass in
configuration directory with *.inc files rather than list of *.h
files.

Change-Id: I3c716e5ad42e55ab3a3a67de1e9bf10e58855540
Signed-off-by: Bartek Pastudzki <Bartek.Pastudzki@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:50:12 +00:00