Commit Graph

16416 Commits

Author SHA1 Message Date
Martin Roth 9df9e93914 arch/x86: add missing license headers
These were mostly written as part of the coreboot project, so get
the standard coreboot license header.

memmove.c came from the linux kernel, so also gets the standard
coreboot v2 license header, but gets the added attribution that it
was derived from the linux kernel.  Unlike many coreboot files,
this file may not be re-licensed as GPL V3.

Change-Id: I1fdc26b543e059f7a42d4b886f7222f4c74b959d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12916
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14 23:37:06 +01:00
Divya Sasidharan 1ff0f54f03 soc/braswell: Add CPUID for D0 stepping
Original-Reviewed-on: https://chromium-review.googlesource.com/309122
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>

Change-Id: Ia24dbeb6b23ccbbb380843a4684def578cde168a
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://review.coreboot.org/12727
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14 23:09:47 +01:00
Martin Roth edb937acd6 ec/: add missing license headers
thermal.asl was written as part of the coreboot project, so gets
the standard coreboot license header.

ec_commands.h came from the chrome ec tree, so gets the BSD license
from that tree as mentioned in the header that has been replaced.

Change-Id: I514138fd4ed236105998b25d1d2d8eb8441cf91d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12918
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14 22:52:51 +01:00
Martin Roth 1766b1ea9d acpi/: add missing license header
These were mostly written as part of the coreboot project, so get
the standard coreboot license header.

Change-Id: Ief13339647d3172e65bb18e6dcb54312a5c9472e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12917
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14 22:52:11 +01:00
Martin Roth a7cf7b7776 arch/x86/include: add missing license headers
These were all written as part of the coreboot project, so get
the standard coreboot license header.

Change-Id: I51e1e504b3bc7be2a00c9356d8775b87f2a1db5a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12912
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-14 22:48:17 +01:00
Subrata Banik 45a221de79 soc/braswell: Fix P-state table
Incorrect bus-core-ratio been used to generate P-state table

Original-Reviewed-on: https://chromium-review.googlesource.com/290681
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I4a34ec80ff3f2ed46dc074c9f8fe06756db8b357
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12731
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14 19:17:01 +01:00
Martin Roth baf00e6b28 intel/skylake/pcr.c: error out on invalid size in pcr read/write
The read and write routines take a number of bytes to write, which
should be 1,2, or 4.  We now return an error if an invalid size
is specified.

Change-Id: I93344bc0837c3715fc7660503f405c8878eb711c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12936
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-14 19:15:58 +01:00
Martin Roth a6e7702787 xcompile: More updates on ARM64 Erratum flags
I tried to handle the checking for the config flag internal to xcompile,
but the config flags don't appear to have been loaded into the
environment by make at that point.

This does update the if to check if the flag is even set before putting
anything into .xcompile though.  If the LDFLAG isn't set, there's no
point in appending anything.

Also removes the LP version of the erratum config flag, which was a
copy/paste mistake from $(CONFIG_LP_COMPILER_GCC).

Change-Id: I3d8b0328c85310393a120741a498bc18867a6f54
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12858
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14 19:14:57 +01:00
Nico Huber 3cbe62fe37 mb/lenovo/x200: Add panel power sequence values
Values are taken from the vendor BIOS of my X200s. Notable effect:
Stops display from flashing during native graphics init / Linux mode
setting.

Change-Id: Ie5d9efc010a78dd46317b6bbdb7bfacc2c9d2cbf
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14 19:08:44 +01:00
Nico Huber b851cc69d6 nb/intel/gm45: Backport configuration of panel power timings
Register settings are the same as on newer chips (compare sandy-
bridge), just at different locations.

Change-Id: Iea0359165074298a376e0e2ca8f37f71b83ac335
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12885
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14 19:07:45 +01:00
Nico Huber c3571da263 nb/intel/gm45: Drop unnecessary panel power handling
Skip everything but the final setting of PP_CONTROL, i.e. triggering
the power up. The settings with PANEL_UNLOCK_REGS are useless as no
lockable registers were touched in between. Also the loop waiting for
the panel power up to finish was a no-op as the registers with the
power timings were never filled (see follow-up commits).

Change-Id: Ife27dcafdf197b2246c4e69f2bf7a3a6765d1d82
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12884
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14 18:57:44 +01:00
Stefan Reinauer 924f0a6421 cbfstool: Change FMAP granularity to 16 bytes
Instead of looking for an FMAP at every byte,  only search down
to a granularity of 16 bytes, reducing the time for a cbfstool
call by 0.3s when no FMAP is found.

Signed-off-by: Stefan Reinauner <reinauer@chromium.org>
BUG=none
BRANCH=none
TEST=time ./cbfstool coreboot.rom add -f locale_de.bin -n locale_de.bin -t 0x50 -c lzma
     is 0.3s faster than before.

Change-Id: Icb4937330e920ae09928ceda7c1af6a3c5130ac7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc92d838ba9db7733870ea6e8423fa4fa41bf8fe
Original-Change-Id: Idbaec58a199df93bdc10e883c56675b419ab5b8e
Original-Reviewed-on: https://chromium-review.googlesource.com/317321
Original-Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
Original-Tested-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/12932
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14 18:44:41 +01:00
Daisuke Nojiri d201e8c38a cbgfx: add error code to cbgfx_init
cbgfx_init can fail for multiple reasons. These codes help debugging
cbgfx_init.

BUG=chromium:502066
BRANCH=tot
TEST=Tested on Glados

Change-Id: Ifaa8d91b058bd838a53faf5d803c0337cb1e082c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4caf2496f3583e133f3f216ec401515c267e6e7b
Original-Change-Id: I84f60dd961db47fa426442172ab19676253b9495
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/315550
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12930
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-14 18:44:20 +01:00
Jimmy Huang b87bb29f4f Makefile: Add 3rdparty to CPPFLAGS_common
In some occasions, Coreboot may need to include the header file from
3rdparty directory. By adding 3rdparty directory to Coreboot include
path, we can include 3rdparty header file directly.

BRANCH=none
BUG=none
TEST=build pass

Change-Id: I8ed68bd330eae1211736a91b213c5dc0af2f7fa9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d6a86b3488ebbc9d8f5f46e922106b71034e7127
Original-Change-Id: Ib8e9f059f88a8c6767f872af8760e91186ae5ec3
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315021
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12929
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-14 18:44:03 +01:00
HC Yen 14ec199bd1 cbfstool: fix address truncated problem
In parse_elf_to_stage(), it uses 32-bit variable to handle address.
The correct address type is Elf64_Addr. Use uint64_t to prevent address
to be truncated.

BUG=none
TEST=emerge-oak coreboot
BRANCH=none

Change-Id: I1abcd16899a69b18dd10e9678e767b0564b2846e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ebc1aae0ae4ca30802a80a4a4e2ae0c0dad4d88a
Original-Change-Id: I21f8057ddf13e442f1cf55da6702c3449ba0cc35
Original-Reviewed-on: https://chromium-review.googlesource.com/292553
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12927
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14 18:43:54 +01:00
Alexander Couzens f8970f53ef mainboard/lenovo: reserve century byte
The century byte is used by most RTC (default 0x32@nvram).
Even the century byte can disabled via ACPI it's more safe to reserve
it's space. Because some RTC will act with that byte anyhow.
Some OS overwrite it when syncronize the RTC.

Change-Id: I078c0c57215ccb925afa85b9d067f15268801ec9
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/11853
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-14 17:58:29 +01:00
Patrick Georgi 485225e0a3 cbfstool: reorder help text
hashcbfs was spliced in a line early, mixing up 'extract' and 'cbfshash'
help texts.

Change-Id: I86d4edb9eec0685a290b2dd4c2dc45d3611eba9a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12922
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-14 10:34:17 +01:00
Martin Roth cf77d28ff7 arch/arm64: add missing license headers
These were all written as part of the coreboot project, so get
the standard coreboot license header.

Change-Id: I4fccc8055755816be64e9e1a185f1e6fcb2b89ae
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12911
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13 22:58:17 +01:00
Martin Roth e44adfa5de arch/arm: add missing license headers
These were all written as part of the coreboot project, so get
the standard coreboot license header.

Change-Id: I74438e8032c84f4190ef49f306969f7157234001
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12910
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13 22:54:02 +01:00
Martin Roth eb20e60c9c utils: Remove old license text from help & disclaimer file
The license text that we decided to remove was removed from the headers
of these files, but was still left in the help text.  Remove it from
those locations as well.

Change-Id: I0e1b3b79f1afa35e632c4a4dd09a8bf2b02eaa6d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12913
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13 22:53:29 +01:00
Martin Roth a20ac2f7b3 tree: drop last paragraph of GPL copyright header from new files
This continues what was done in commit a73b93157f
(tree: drop last paragraph of GPL copyright header)

Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12914
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13 20:35:40 +01:00
Martin Roth 02ec8feb2c intel/skylake platforms: Add MAINBOARD_HAS_LPC_TPM in Kconfig
Because these platforms haven't been getting build testing, they've
missed out on some of the improvements that the other platforms have
gotten.

Enable MAINBOARD_HAS_LPC_TPM so that they will build.

Change-Id: I5e44135b6dfa800fa14e5b08c3e3e5921d50b082
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12865
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13 19:56:50 +01:00
Patrick Rudolph a696ae7e30 intel/northbridge/sandy: raminit code cleanup
Remove redundant call to dram_mrscommands().

Change-Id: I157915b4432093c556b538433e3337db1e9c525f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12891
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13 17:58:52 +01:00
Nico Huber 498e315988 [WIP] mb/roda/rk9: Enable CONFIG_HAVE_ACPI_RESUME
Change-Id: Ifa7dd593f70921a99d937104960e26100de28089
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12421
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13 17:53:27 +01:00
Martin Roth cbe38923d9 northbridge/intel/x4x: clean up includes
- Don't redefine D0F0_PCIEXBAR_LO, use the #define in x4x.h
- Move TPMBASE and TPM32() definitions into iomap.h
- Use "" style include for x4x.h in nortbridge files.
- Move includes of .h files out of x4x.h and into the c files that need
them.
- Protect function definitions in bootblock.

Change-Id: I3fdb579235c5446733a0ffba05fffe1a73381251
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12849
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13 17:52:46 +01:00
Werner Zeh d274c99ad7 cbfstool: Remove duplicate code line
Remove duplicate line which sets baseaddress parameter.

Change-Id: Idfbb0297e413344be892fa1ecc676a64d20352bf
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/12904
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-13 06:07:29 +01:00
Martin Roth daa9e12bc5 util/lint: Add lint script to run kconfig_lint
The lint target in the makefile relies there being a script using
this particular naming format, so add a shell script front end to
run the kconfig linter.

Change-Id: I029c1cd3bbf3837c9f1d86c391ae5cabfa53685d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12903
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-12 22:33:12 +01:00
Martin Roth 1b44f7e390 util/lint/kconfig_lint: Run through perltidy to fix whitespace
Change-Id: I7f04156fff0b65ea262b12961ce76ef329d358ab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12902
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-12 22:32:45 +01:00
Martin Roth 0ecbdde285 lint: rename lint-006-checkpatch because board name is lint-006
Checkpatch should be 007.

Change-Id: Ib71c50ad1a63a3a743391cd8fea9f79cd08ef6f3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12901
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-12 22:32:16 +01:00
Martin Roth aede3fc828 Makefile: Add toolchain version check
This is an initial check for the coreboot toolchain versions.  It
currently checks binutils, gcc, clang, and iasl.  The other components
are slightly more difficult to test, but should follow on shortly.

If the toolchain is not the correct version, make will halt with
an error.

Change-Id: I41daf6c4545c01dc21231d78fd081bbcf77c4726
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12846
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
2016-01-12 22:31:30 +01:00
Martin Roth 5933814e27 amd/cimx/sb800/pci_devs.h: Update guard #define name
Change-Id: Ieae41cab97293831a0c49c3b472b9e6c62ba36c6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12899
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-01-12 22:24:52 +01:00
Martin Roth 5559e8935e intel/skylake: Remove check for Microcode loaded by ME
This method of reporting has been removed from the current Skylake
ME binaries so is no longer needed.

Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12854
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-12 22:24:09 +01:00
Matt DeVillier 8e6b0a2ae2 google/guado: initial upstream migration
Migrate google/guado (Asus Chromebox CN62) from Chromium tree to upstream,
using google/auron and google/panther as refs.

TEST=built and booted guado with full functionality

Change-Id: If7a500fb408197a61c9619b9d5ea1458d1f4d702
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12800
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-12 22:20:28 +01:00
Werner Zeh 2de6410eee Makefile: Correct spelling in help message
Correct wrong spelled "subnit" in help message.

Change-Id: Iadbf483835ee4c1b6e3faa454d1cae2660b99c5e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/12905
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-12 22:19:45 +01:00
Nico Huber ee352cdcca nb/intel/gm45: Convert gma.c to `if (IS_ENABLED(` style
Change-Id: Ifae3822b6c28832f6aa05a4ffd8f02067a923f2c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12883
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-12 13:50:11 +01:00
Vladimir Serbinenko 6b2d83c352 autoport: Add missing casts
Change-Id: I04abdd48f5e2440756f9b03041d46c773f200368
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/12890
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-01-11 20:51:12 +01:00
Martin Roth 229d427c12 fsp1_1: Remove #if protection in header - It's not needed
There's nothing in these files that needs to be hidden if
GOP support is disabled.  Removing this allows skylake to
build when GOP support is turned off.

Change-Id: I2a4f47cd435f48668311719f388b502ae77eca99
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12859
Tested-by: build bot (Jenkins)
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-01-10 23:38:23 +01:00
Marian Tietz 7c6c4df68c lenovo/x220: Enable USB 3 controller
Since only X220 with i7 have the USB3 controller this was
probably overlooked.

Before this patch lspci on Linux would not show the NEC USB 3 controller
as well as the PCI bridge it is behind. After, both the bridge and the
NEC controller can be found in the output:

    05:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller
	(rev 04)

Change-Id: I5e7e3f0c7d023f6206a7bec42a39f8955a3d9331
Signed-off-by: Marian Tietz <mtcoreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/12882
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-01-10 18:48:12 +01:00
Martin Roth 8846382cbb buildgcc: Print out all missing tools then halt
Instead of printing out a single tool that needs to be installed
each time buildgcc is run, print out the entire list of tools
to be installed, then halt.

Change-Id: I7761760eef3c45ba371f882a4f987408945bb3e5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12856
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-09 22:18:59 +01:00
Martin Roth fecc24af04 vendorcode/amd/agesa/f15tn: Fix out of bounds read on on memory voltage
I think this has a fairly low likelyhood of happening, but if AGESA
can't determine the voltage of the memory, it assignes a value of 255
to the variable that it later uses to read from an 3-value array.  There
is an assert, but that doesn't halt AGESA, so it would use some random
value.  If the voltage can't be determined, fall back to 1.5v as the
default value.

Fixes coverity warning 1294803 - Out-of-bounds read

Change-Id: Ib9e568175edbdf55a7a4c35055da7169ea7f2ede
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12855
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-08 17:21:59 +01:00
Martin Roth b95a074586 fsp_baytrail: Add additional PCI space above 4GB
This just tells the OS that it can use the 16GB of address space
at the 48GB mark for PCI.  This is the upper 16GB of Bay Trail's 36 bit
physical address space.

This could be hardcoded into the UMEM definition, but doing it this way
makes it more plain what it's doing, and allows for modification
to put it just above the top of upper memory, similar to what is done
with the standard PCI region above the top of low memory.

Change-Id: Id6208c3712e5d94d62a83c4ac69e8ffd0e19f4ad
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12791
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: York Yang <york.yang@intel.com>
2016-01-08 02:44:15 +01:00
Martin Roth 481a19cf99 intel/braswell: Disable IFD & ME by default so abuild can build
The Braswell IFD & ME blobs aren't published in the 3rdparty repo, so
disable them by default for now.

Change-Id: If68ff1f37fbf7afb2f9eb1e5d9942afcf40ab1e3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12828
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07 23:04:31 +01:00
Stefan Reinauer 9dbdf520d8 mainboard: Drop abuild.disabled files for Braswell boards
Make sure the latest & greatest Intel targets actually
build in our build system.

Change-Id: I479ad473c260fc914d224cb58f4be1837aff2502
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12463
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 23:01:39 +01:00
Martin Roth e396317244 buildgcc: Don't request that optional tools be installed
Previously, when we tested for g++ and two different versions of clang,
if the earlier versions were not found, buildgcc would still request
that they be installed.  This obviously isn't needed, and isn't the
desired outcome.
Now, if one of the first tests fails, nothing gets printed.  If all
the tests fail, it tells you to install either g++ or clang.

Change-Id: I71359f59c4c6bee3c3c55e4e6105f11e6ca51527
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12852
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 22:59:02 +01:00
Martin Roth 2ed0aa258f Correct some common spelling mistakes
- occured -> occurred
- accomodate -> accommodate
- existant -> existent
- asssertion -> assertion
- manangement -> management
- cotroller -> controller

Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12850
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07 22:57:02 +01:00
Paul Menzel 2e0d9447db src/vendorcode/amd: correct spelling of MTRR
Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/4806
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-07 17:40:45 +01:00
Stefan Reinauer f8532b16be f14: Increase AP stack to 8k on 64bit
This has been broken out from http://review.coreboot.org/#/c/10581/

Change-Id: Ia6153115ff75e21657fa8c244c9eb993d0d63772
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://review.coreboot.org/11025
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 17:39:13 +01:00
Martin Roth 24ca41d074 google/cyan, intel/strago Kconfig: Only ask to display SPD once
Change-Id: Ic3df9bf7d7f3c4c39789f3f496bcb7fc2ee50931
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12827
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 17:34:26 +01:00
Martin Roth 2ba837d8c7 xcompile: Quote variables to prevent globbing and splitting.
Quoting variables prevents word splitting and glob expansion, and
prevents the script from breaking when input contains spaces, line
feeds, glob characters and such.

See shellcheck warning SC2086

Change-Id: Ib6ca46b64a621c4bea5c33ac312f2824b0386235
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12845
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 17:28:44 +01:00
Martin Roth 7051dea5f4 xcompile: Use local variables in the test functions
Using the local variables instead of positional parameters helps
readability.
- Add and use the local variables in testcc.
- Use the existing local variables in testld.

Change-Id: Ice13288b830a7aa043b360eaee8e36f060589a18
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12844
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 17:24:50 +01:00