The old name was misleading, since it doesn't disable the generation of
SMIs, but clears the status registers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iddadbec013091c2e5993a6303e291451c3d1e7ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50459
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add comments to mem_parts_used.txt to point out that the order of
the entries matters when assigning IDs, so always add a new part
to the end of the file.
* Update existing mem_parts_used.txt to add the same comment.
* No updates to Zork variants, because they use an optional ID, so
the order actually doesn't matter there.
BUG=b:175898902
TEST=create a new variant of dalboz, trembyle, volteer, waddledee,
or waddledoo, and observe that mem_parts_used.txt has the new
verbiage.
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This also aligns Stoneyridge with Picasso and Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I35bf9915e3502c22e9dd9efa80b00a1ce70f187d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50436
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setup the config required to support verstage.
The offsets are the same as picasso.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Required so we pass SPI information down to depthcharge.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4ce819b537333c28d394c925331e3dbf260b7732
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The picasso SPI registers are different than the ones defined in
amdblocks/lpc.h. The BASE_ALIGNMENT has changed and the
PSP_SPI_MMIO_SEL bit has been added.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0b5a0c88c6dbb95cdbc62b949a7d30bfad1fa725
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This is a copy/paste of amdblocks/lpc.h. The registers are different for
picasso and cezanne, so I'm moving them to soc.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4dfadcdc025d3581cb1423e9793a9b2181742b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
PEP table is applicable to Skylake platform as well. It is required to
make the kernel load `intel_pmc_core`. Skylake boards can also use S0ix
hooks.
Tested on an out-of-tree Acer Aspire VN7-572G (Skylake-U),
intel_pmc_core kernel module is loaded and reports statuses predictably
via debugfs.
Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49140
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The transfer buffer is only required when using
VBOOT_STARTS_BEFORE_BOOTBLOCK.
The VBOOT workbuffer is only required when VBOOT_STARTS_BEFORE_BOOTBLOCK
or VBOOT_STARTS_IN_BOOTBLOCK.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I444bede3f2b716e1900e7621453351d7fddadaa3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
EDGE IRQ from TS might be invalid to HOST, configure IRQs
as level triggered to prevent TS lost.
BUG=b:179594439
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
2. power on, suspend DUT to check TS is functional
Change-Id: Ibbbc73b37932ba1359ffe6f572a15564bb341025
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50416
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
southbridge.c was renamed and split into early_fch.c and fch.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie439e746fb3dfe9ec865481a76a09eab378242bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50458
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since Jelboz support number pad,
due to one single coreboot for both Jelboz and Shuboz,
modify "overridetree.cb" setting to number pad support for Jelboz.
BUG=b:174964012
BRANCH=master
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie0219419834b34b6eac589f28d3604f5f1b65679
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
If the PSP didn't like a command this should be at least a warning on
the console and not just a debug message.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7e5f6320631cca86813e98f82b8c0c21bf18af1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reduces the differences between Lynx Point and Broadwell.
Change-Id: Ib53d73e3f89c538ba0f052a98c7aabe815a59472
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46891
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SCI IRQ is always set to IRQ 9 in the bootblock. To allow using
common MADT code on Broadwell, hardcode it as 9 everywhere.
Change-Id: I84345b7985b1996369cecc4bcb0a3668d002a922
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The lb_gpio coreboot table entries use name fields fixed to 16 bytes.
GCC will not allow creating a static initializer for such a field with a
string of more than 16 characters... but exactly 16 characters is fine,
meaning there's no room for the terminating NUL byte. The payloads (at
least depthcharge) can deal with this as well because they're checking
the size when looking at that table entry, but our printk("%16s") does
not and will happily walk over the end until somewhere else in memory we
finally find the next NUL byte.
We should probably try to avoid strings of exactly 16 characters in this
field anyway, just in case -- but since GCC doesn't warn about them they
can easily slip back in. So solve this bug by also adding a precision
field to the printk, which will make it stop overrunning the string.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ifd7beef00d828f9dc2faa4747eace6ac4ca41899
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable acoustic noise mitgation for volteer platforms.
BUG=b:179328166
BRANCH=none
TEST= Measure the change in noise level by changing the values
in devicetree.
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I279a85c7741094bb7ddf0c1fde74b31189b12171
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This change uses the following information to determine the
appropriate S0ix states to enable as per PDG document: 607872
for TGL UP3 UP Rev2p2 (section 10.13):
1. SoC - UP3 v/s UP4
2. H/W design - external phy gating, external clk gating, external bypass
3. Devices enabled at runtime - CNVi, ISH
In some cases, it is recommended to use a shallower state for
S0ix even if the higher state can be achieved (e.g. with external
gating not enabled). This recommendation is because the shallower
state is determined to provide better power savings as per the
above document. Deepest state expected on tigerlake up3 based
platforms is S0i3.2.
BUG=b:177821896
TEST=Build coreboot for volteer. Verify that deepest
S0ix substate that is enabled is S0i3.1
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49766
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Felix Held