The function read() returns the number of bytes actually read. Program is
assuming it actually read the required number of bytes without checking.
This is wrong.
This fixes CIDs 1353019 and 1353021
BUG=b:72062481
TEST=Build no errors
Change-Id: I22d41b3de4eac5369f512f78b1b31cc1a250f787
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
File open function <open()> will return -1 if there's any error. Check that
the return is greater or equal to 0 before using fstat(). Print error message
and exit if there's an error.
This fixes CIDs 1353018, 1353020, 1353027 and 1353028
BUG=b:72062481
TEST=Build no errors
Change-Id: I77d6973d1ad1eadb93922866e618038045be5937
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The AMD firmware directory can go in a number of different locations.
This patch allows amdfwtool to write the directory correctly for those
different locations.
If the --location switch is not added to the command line, the default
location at ROM base address + 0x20000 is used as before.
BUG=b:65484600
TEST=Set PSP firmware location, compare amdfw.rom to previously built
version. Verify new location pointers.
Change-Id: Ief32e5e37d56088946b623d305c6e93bfd6abeaf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the images around in the image stitching. This addresses
an issue found with PSP firmware loading on the Google Kahlee
mainboard.
Note firmware1 must come before firmware2 in the image or
the PSP will not allow APU to execute.
Change-Id: I85963fa93d6efd707cedfbc04b92d302ad5de3b1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19170
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The Stoney Ridge program has OPNs that are considered fanless. These
APUs are strapped to search for unique SMU firmware, indicated by
Type[8]=1 in the directory table entry.
Add new options to amdfwtool and include the blobs in the build with
the appropriate bit set in the Type encoding.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 8df0d6847c39bb021271983018ac6f448f9ff9da)
Change-Id: I4b80ccf8fd9644f9a9d300e6c67aed9834a2c7a7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18991
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
- Return an error if the specified file could not be opened. To do this
cleanly, the return value was added.
- Since there's now a unified return value, use it where it makes sense.
- Don't return an error from --help. If you've asked for usage, it's
not an error.
Change-Id: I7c712d1e1927c2d4957b044b87ad26475b7a0e3b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17324
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Various fixes for clang warnings:
warning: arithmetic on a pointer to void is a GNU extension
- change *rom from void* to char* and cast back to void* as needed
warning: implicit conversion changes signedness
- In ALIGN macro, pass in value as unsigned
warning: no previous prototype for function
- Change functions to static
warning: no previous extern declaration for non-static variable
- Change global variables to static
warning: comparison of integers of different signs
- Make loop variable 'i' unsigned
warning: variable 'output' may be uninitialized
- Make sure an output filename was specified
warning: implicit conversion loses integer precision
- cast fd_stat.st_size to the appropriate type
Change-Id: I0134a79c00938e121e63b52fd63bd502f4cb9e99
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17322
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Previously, the ROM size was passed into amdfwtool solely as a #define,
meaning that all boards built with the tool would assume the same size
ROM. This became a problem when the default rom for abuild was updated
to be a board with a 256KB ROM.
The temporary solution was to build amdfwtool individually for each
board that needed it. This replaces that workaround by allowing the
ROM size to be passed in as a command line parameter.
- Add the -f | --flashsize option to accept a hex value for the ROM
size.
- Add checks to make sure the ROM size supplied is large enough.
- Because the ROM size is not hardcoded, it needs to be passed to
various functions.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615
Reviewed-on: https://review.coreboot.org/17321
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Double the space for psp2dir to 0x200.
Based on advice from AMD, increase the region containing
the signature to 4K.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit e03a9402711c3a210816d0aa32865491a0523639)
Change-Id: If60132f913928bab0c2fe4aacedf342080929599
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17148
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit 482b65c219b932fd374f2ac469a023db219a66de)
Change-Id: I0a24a0aa4c7d9f4a8cc3ee9b7da60ea7704e6f17
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17147
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
Make the PSP2 smufirmware2 name unique so the command-line option
gets picked up.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: <marcj303@gmail.com>
(cherry picked from commit 98cf3880797f72aeb7169c3f8718a10092af9624)
Change-Id: I5430cf8b81fb03c95e6ee9d7e53455e6224256ff
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17146
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
1. Change the function which integrated one firmware, to the function
which pushes the whole group. Use fw_table as a parameter instead
of using the global table name.
2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2
can exist without PSP1. For some APU, the PSP directory has to be
put in PSP2 field (ROMSIG 0x14).
3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It
is tested, and it is true.
These above changes are overlapping, hard to split them. Sorry.
Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/13808
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
If we only need to "combo" two PSP directories into one image,
we can put first address in romsig 0x10 and second one in
romsig 0x14.
If we really need to put three, the 0x14 is the combo directory
which points to multiple level-2 PSP directories.
I guess that two PSP can also use combo directory, with only
one level-2 directory. But nobody seems to do that.
Change-Id: Ic450a846bc04db90a75cd417b6d7104fe2a5b177
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/13739
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
I didn't go back through the development guide for this.
But based on test, if the empty entry is filled as 0xFFFFFFFF,
instead of 0, the USB3 port can not be used.
Leave the entries of PSP and PSP2 as 0xFFFFFFFF to be compliant
with the case before the amdfwtool is used.
Change-Id: Icd5f9891e541279dbd551bbceaf091488d22bfef
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/12665
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
PSP2 is for Combo BIOS, which is the idea that one image supports 2
kinds of APU.
The PSP2 feature is for the future, not for current products.
The newest document about PSP2 is not available. I made it from the
draft code I made when I was in AMD.
Change-Id: I65328db197c02ee67f3e99faf4ab8acabd339657
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/12474
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Combine all needed AMD firmware into one single firmware, which going to
be added as one single CBFS module.
Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12419
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Richard Spiegel