Commit Graph

30053 Commits

Author SHA1 Message Date
Kyösti Mälkki 4d372c7353 cpu/x86: Declare SMM_ASEG
This is really an inverse of SMM_TSEG to flag
platforms that should potentially move away
from ASEG implementation.

Change-Id: I3b9007c55c75a59a9e6acc0a0e701300f7d21f87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-09 12:48:01 +00:00
Kyösti Mälkki 328d42f2d8 cpu/intel: Drop SMM_TSEG conditional
SMM_TSEG is a qualifier between TSEG and ASEG memory
region. ASEG is deprecated and not supported for
these CPUs in coreboot codebase.

Change-Id: I0602e04957a390473a2449e1c5ff951f9fdff73b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-09 12:45:48 +00:00
Kyösti Mälkki 8f076f2be8 soc/amd/stoneyridge,picasso: Switch SMM lock condition
SMM_TSEG is a qualifier between TSEG and ASEG memory
region. ASEG is deprecated and not supported for
this platform in coreboot codebase.

The SMM lock should be set based on whether SMM is
installed or not, HAVE_SMI_HANDLER currently tells
that.

Change-Id: I9756f8a59ccfedd59d5b997b35313452dd0c4f46
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34127
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09 12:44:39 +00:00
Kyösti Mälkki 60012ac64e arch/x86: Replace some uses of SMM_TSEG
No reason why the files could not be used with ASEG.
Attempts to use malloc() from ASEG would still fail,
though, due the lack of heap.

Change-Id: Idf470ae84eb34c442e833925510b08d5314e7638
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34126
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09 12:44:10 +00:00
Kyösti Mälkki 9265f89f4e arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class
Build of the entire smm-class is skipped if we have
HAVE_SMI_HANDLER=n.

Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09 12:43:35 +00:00
Subrata Banik cb587a2522 drivers/intel: Move FSP stage_cache implementation into common block
Change-Id: Iebb6d698c236a95162b3c7eb07987483a293b50a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-09 10:52:33 +00:00
Subrata Banik df29d23ee3 soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h
Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34085
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09 10:52:19 +00:00
Nico Huber 45564050ec crossgcc: Fix runtime initialization of a constant
GNAT had a constant initialized at runtime which led to trouble
with compilers that decided to place it into an actual constant
section (e.g. GCC 9). Usually, this would be handled gracefully
if the Ada compiler knew about the runtime initialization. How-
ever, as the initialization was done by taking the address of
the variable, the compiler had no clue.

Change-Id: I73ce4cadc612c814ed2e22b44f429af2ad3db288
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34147
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09 10:42:08 +00:00
Patrick Rudolph 674bb3bf65 util/superiotool: Add AST2400
Add support for AST2400 Super I/O.

The device doesn't have an ID register, so probe for scratch register
not to read as 0xff.

Tested on platform which has an AST2400.

Change-Id: I86af69c6b2ccefe2c88eef875bc858239df834f1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-08 16:13:29 +00:00
Arthur Heymans a3121b0b2f sb/intel/lynxpoint: Use common final SPI OPs setup
Change-Id: I12e238b3a33c909103986822bd7398e1c3bac676
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-08 14:54:54 +00:00
Arthur Heymans aadd1d0eaf sb/intel/ibexpeak: Use common final SPI OPs setup
This also removes the relevant RCBA replays the mainboard dir.

Change-Id: I75dd9d1bcd09d835f205a51c087d52ebb4e166f6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Thomas Heijligen <src@posteo.de>
2019-07-08 14:54:13 +00:00
Arthur Heymans b429c5be15 sb/intel/i82801gx: Use common final SPI OPs setup
Change-Id: I30f80c237bccf8dc350249fd12ca6c4559d23d4f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-08 14:53:32 +00:00
Arthur Heymans 92185e373e sb/intel/common: Add a common interface to set final OPs settings
This adds a common place to set the final opprefix, optype and opmenu,
with a hook to override the opmenu.

Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-08 14:52:54 +00:00
Elyes HAOUAS 3fcea0dfad cpu/x86/smm/smm_module_loader: Compare num_concurrent_stacks to size_t
Spotted out using -Wconversion gcc warning option.

Change-Id: I11e4792804f0f7b5a7ce504c46654c1bff775c32
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-08 14:51:49 +00:00
Elyes HAOUAS cca6e00868 src/arch/x86/acpigen: Compare dev_states_count to size_t
Spotted out using -Wconversion gcc warning option.

Change-Id: Ib882cfa6d429fbfcab2b8132280182b427d510aa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33803
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08 14:51:08 +00:00
Patrick Rudolph fbdeb4af75 qemu-q35: die if started on wrong machine
The QEMU machine "PC" doesn't support MCFG.
Die after console init if the user selected the wrong qemu machine
and print a message to use the correct machine type.

Without this patch ramstage dies with non-helpful message:
"get_pbus: dev is NULL!"

Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-08 14:50:12 +00:00
Kyösti Mälkki 26210fa040 intel/socket_mPGA604: Enable TSC_MONOTONIC_TIMER
Change-Id: I3ca2b7752905209e8db6b1dc74b930445676792e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-08 09:47:15 +00:00
Kyösti Mälkki b14aedc3ad intel/nehalem: Move TSC_MONOTONIC_TIMER
Change-Id: Ib7f2f7773d0eef5ac4e277b44ee9114aa6729527
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-08 09:46:57 +00:00
Kyösti Mälkki f2a66d2b0c intel/fsp_broadwell_de: Remove redundant TSC_MONOTONIC_TIMER
Change-Id: I240e9e767c9b38b3b06d3978fd20ddb37a96e470
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-08 09:46:40 +00:00
Kyösti Mälkki c804f31a13 intel/fsp_baytrail: Move TSC_MONOTONIC_TIMER
Change-Id: Ib61ea29724401146eb6f008374cdf599f418e81f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-08 09:46:21 +00:00
Kyösti Mälkki f8c3442df0 drivers/pc80: Move UDELAY_IO and UDELAY_TIMER2
No longer fallback to UDELAY_IO as default.
Since these are not cpu properties or features,
move the Kconfig location.

Change-Id: I9809cdc285c7bf741aa391ddb5755390bbfc2909
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-08 09:45:56 +00:00
Martin Kepplinger af15d040e1 payloads/external/Memtest86Plus: update to version 002 stable
The memtest86plus project has been tagged as stable. Update the coreboot
build accordingly.

Change-Id: I078ac5d91e60a424efb5e14f39ae59e7ae9cbfe2
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-08 07:54:13 +00:00
Frank Wu 3076deb391 mb/google/hatch: Set GPP_D9 as enable pin for Goodix Touch Screen and
increase reset off delay time

Goodix touchscreen cannot work in normal mode because PP3300_TOUCHSCREEN_DX
dropped. Configure GPP_D9 as enable pin in the devicetree.cb to fix the power
sequence. Increase reset_off_delay time from 1ms to 3ms to met the HW requirement.

BUG=b:135287161
BRANCH=None
TEST=local build and measure sequence with Goodix touch screen

Change-Id: I33140869990aa4715c780b0fa322921e450530ef
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33808
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08 02:13:43 +00:00
Krishna Prasad Bhat c2f6c1d544 mb/google/hatch: Update GPIO settings for SD card and SPI1 Chip select
This patch updates the following GPIO settings.
1. Set Native termination for GPP_G0 - G4 SD card pins.
2. Set GPP_B19 to NF1.

BUG=b:123907904
TEST=Verified SD card functionality on hatch. Checked for SD detection,
transferred files to and from SD card.

Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-07 23:25:29 +00:00
Kyösti Mälkki 78561f481e lib/romstage_stack.c: Remove file
After platforms have moved to POSTCAR_STAGE=y the only
remaining user is binaryPI now. Make it simpler.

Change-Id: Ia70c5c85e06c42f965fb7204b633db9b619e2e84
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-07 21:27:22 +00:00
Weiyi Lu eb5e47dd94 mediatek/mt8183: update dcxo output buffer setting
DCXO consists of core that generates clock and output buffers that
provide clock to other peripheral components.
This patch mainly eliminates the extra power consumption of output buffers.
We only enable the buffer for SOC and disable unused buffers for power-saving.
Also disable useless buffer power mode to guarantee the lowest power state.

BRANCH=none
TEST=Boots correctly on Kukui.

Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32323
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07 21:04:21 +00:00
Arthur Heymans 142258c2f6 arch/mips: Make MIPS specific options depend on ARCH_MIPS
Also don't define the default as this result in spurious lines in the
.config.

TEST: The generated config.h remain exactly the same for all boards.

Change-Id: I7f35a5a9dcbc7b25b7806056e2b8e822fa94e428
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-07 20:59:55 +00:00
Jacob Garber 2d58bf6a03 util/cbfstool: Prevent overflow of 16 bit multiplications
Considering the following integer multiplication:

    u64 = u16 * u16

What on earth, one might wonder, is the problem with this? Well, due to
C's unfortunately abstruse integer semantics, both u16's are implicitly
converted to int before the multiplication, which cannot hold
all possible values of a u16 * u16. Even worse, after overflow the
intermediate result will be a negative number, which during the
conversion to a u64 will be sign-extended to a huge integer. Not good.

The solution is to manually cast one of the u16 to a u32 or u64, which
are large enough to not have any overflow and will prevent the implicit
conversion. The type of the u64 is preferred, though a u32 is used
instead of size_t, since that can change depending on the platform.

Change-Id: I5391221d46d620d0e5bd629e2f9680be7a53342e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 12297{03,04,05,06,07,08,09,10}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-07 20:59:04 +00:00
Jacob Garber 96e0ce30db util/nvramtool: Mark out_of_memory() as noreturn
This silences several false positives from scan-build.

Change-Id: I327a967c75d6aeec0b3aba16ee696dbae8cf997d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-07 20:55:59 +00:00
Jacob Garber b592917dcf util/nvramtool: Enable -Wmissing-prototypes
Change-Id: Id751250b07a495dc25293ff703602bfefa9011bd
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:54:04 +00:00
Jacob Garber f2a2137ae2 util/nvramtool: Make internal function static
This function is only used in this file, so it can be made static.

Change-Id: I90e673da91eb926424d1730c268860da7fa1627b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:26:44 +00:00
Jacob Garber 4177bedd65 util/nvramtool: Include missing header
The prototype for is_ident() is in this header, so include it.

Change-Id: I45e0d58d1b891b18b3eb7741897ab691188a2bd9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:26:25 +00:00
Jacob Garber f2ba2d9421 arch/x86: Use ssize_t to store length
size_t is the wrong type to store the return value of
acpi_device_path_fill(), since any negative error values will be
converted to a very large unsigned integer and potentially cause
buffer overflow.

Change-Id: Ia8ed62ecfac8eaa18a61545bd203b3c7a7cd9ca5
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1402095
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-07 20:25:12 +00:00
Kyösti Mälkki 3c2305f162 drivers/amd/agesa: Drop redundant stack allocation
The removed call was there to support case LATE_CBMEM_INIT=y,
HAVE_ACPI_RESUME=y. Same stack space is already allocated
with postcar_frame_init() call.

Change-Id: I03a44bc3252f553b1769d362b2f442d3e6ab73f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-07 20:24:39 +00:00
Jacob Garber 57f2188d86 util/inteltool: Enable -Wmissing-prototypes
Change-Id: I6bf041d089498780ea2b7c52402d7452d44d3f87
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33946
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07 20:23:55 +00:00
Jacob Garber 6faccd1f00 util/inteltool: Make internal functions static
None of these functions are used outside of the files they are defined
in, so they can all be static.

Change-Id: Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:23:42 +00:00
Jacob Garber e2e8ccefd7 payloads/coreinfo: Enable -Wmissing-prototypes
Change-Id: I7ee9436ba71ceea35a35272291ea245c0b7c37c5
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:21:09 +00:00
Jacob Garber 609305fa76 payloads/coreinfo: Make internal functions static
These functions are only used in the files they are defined in, so they
can be made static.

Change-Id: Ic7f78912803cbdd1cb3a75f7f69f526739dab6e7
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:20:44 +00:00
Jacob Garber 729d5971d2 payloads/coreinfo: Enable -Wextra
This enables extra useful warnings.

Change-Id: I3d54988935c7df9ac0dc2f7aceb56fb720c9c4d1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:20:20 +00:00
Jacob Garber a711e9c44d payloads/coreinfo: Use correct integer types for loop indices
Make sure that the type of the loop index matches the type of the upper
bound. This fixes several -Wsign-compare warnings.

Change-Id: I73a88355d86288609e03f7a6fcaec14dfedac203
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:19:49 +00:00
Jacob Garber 37bec0b397 payloads/coreinfo: Use fixed-width integers for cpuid
This function executes the cpuid instruction, which takes a 32 bit input
value (idx), and then stores output in eax, ebx, ecx, and edx, which are
all 32 bit registers. Update the prototype to use fixed-width integers,
and update all usage calls appropriately.

Change-Id: I15876fa35628d3a505864fb49be4fdab1fd19f4a
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:19:05 +00:00
Sukerkar, Amol N 598af2e2c2 src/security/vboot: Add option to skip display init with vboot 2.0
This config option, when set, will allow the platform to skip display
initialization in normal (non-developer, non-recovery) mode. This allows
platforms that do not implement firmware UI in normal mode to skip the
display init in firmware.

TEST=Set option CONFIG_VBOOT and clear CONFIG_VBOOT_MAY_SKIP_DISPLAY_INIT
     and the display should initialize in ramstage when platform boots. Set
     CONFIG_VBOOT and set CONFIG_VBOOT_MAY_SKIP_DISPLAY_INIT and the display
     initialization should be skipped in coreboot.

Signed-off-by: Sukerkar, Amol N <amol.n.sukerkar@intel.com>
Change-Id: Icadad6da34dcb817af02868e89a94ea62dbfa7b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-07 20:09:24 +00:00
Kyösti Mälkki fffc9f3b9d device/pci: Declare pci_root_bus()
This is used a lot, cache the result so search
of domain from devicetree is only done once.

Improvement only applies when MAYBE_STATIC evaluates
to static.

Change-Id: If675abb632fe68acd59ba0bdfef854da3e0839a9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-07 20:04:44 +00:00
Kyösti Mälkki b72b5d9528 arch/x86: Clean up PIRQ_ROUTE
This code is currently only used by via/epia-m850,
it is also somewhat buggy.

Change-Id: I140e15d584d3f60f7824bcb71ce63724c11e3f46
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34078
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07 20:03:55 +00:00
David Wu 3a2660e489 mb/google/hatch/var/kindred: Add Raydium touchscreen support
Add Raydium controller

BUG=b:135728282
BRANCH=master
TEST=
1. FW_NAME="kindred" emerge-hatch coreboot chromeos-bootimage
2. boot up on kindred DUT to check touchscreen device by evtest
   /dev/input/event3:	Raydium Touchscreen
3. Raydium TS is working

Change-Id: Id963300ab0dadcb78786c5a1328c2a4098a48a05
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33857
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07 20:02:40 +00:00
David Wu 5526e68f15 mb/google/hatch/var/kindred: Update ELAN GPIO/IRQ and add Synaptics Touchpad
Update ELAN GPIO and IRQ setting and add Synaptics Touchpad

BUG=b:132708463
BRANCH=None
TEST=Verify ELAN/Synaptics touchpad is working fine.

Change-Id: I883ce2e50ca5c6bd2b1ca76cbe24177055cc5d60
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-07 20:02:27 +00:00
David Wu 21f1ccce9c mb/google/hatch/variants/kindred: Enable eMMC support
Enable eMMC support for kindred.

Cq-Depend: chromium:1666982
BUG=b:135464155
BRANCH=none
TEST=Boot kindred onboard eMMC.

Change-Id: I040af6da30313f8dd59e3ef910b290922e090cdc
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33618
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07 20:02:12 +00:00
Subrata Banik ebdafdb1a7 soc/intel/icelake: Remove redundant gpio.c from Makefile.inc
Change-Id: Ibddc2363e9bfea9ae41e4807435acb2e788dcb93
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-07 13:23:46 +00:00
Mike Banon 87fe418172 mb/lenovo/g505s: Disable SeaBIOS options unsupported by hardware
G505S doesn't have any SAS or NVMe controllers and couldn't have a TPM,
so it makes sense to disable the related SeaBIOS options for this board.
This reduces the size of compiled SeaBIOS by 129344-110048=19296 bytes.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ib0183b7786ecd77bb0df923bc84908275f2fe14c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33870
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07 10:30:19 +00:00
Kyösti Mälkki 142b10ee1f cpu/x86: Fix MSR_PLATFORM_INFO definition
While common to many Intel CPUs, this is not an architectural
MSR that should be globally defined for all x86.

Change-Id: Ibeed022dc2ba2e90f71511f9bd2640a7cafa5292
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
2019-07-07 09:38:06 +00:00