Commit Graph

506 Commits

Author SHA1 Message Date
Elyes Haouas 5331462e9e libpayload: Use __func__ instead of old __FUNCTION__
Change-Id: Ic3c22ac101a2ff44f97b2ac3fe3c0a89391718de
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17 16:19:44 +00:00
Thomas Heijligen 3f9613bf6d commonlib/bsd, libpayload: Do not include helpers.h in stddef.h
`stddef.h` should only provide the definitions defined by ISO or Posix.
The included `commonlib/bsd/helpers.h` provide a lot of non standard
definitions that may interfere with definitions from the application.

Change-Id: Ia71edbc3ffe6694ff4b971decf3a41f915264bc8
Signed-off-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70116
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16 17:55:37 +00:00
Thomas Heijligen 3d91563c98 libpayload/string: add strndup() function
Change-Id: Ie509e49f21fb537692704ac6527efa09649164e3
Signed-off-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70115
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-16 17:54:51 +00:00
Arthur Heymans ea1e36694d coreboot_tables: Drop uart PCI addr
Only edk2 used this to fill in a different struct but even there the
entries go unused, so removing this struct element from coreboot has
no side effects.

Change-Id: Iadd2678c4e01d30471eac43017392d256adda341
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-26 14:12:06 +00:00
Julius Werner d96ca24652 cbfs/vboot: Adapt to new vb2_digest API
CL:3825558 changes all vb2_digest and vb2_hash functions to take a new
hwcrypto_allowed argument, to potentially let them try to call the
vb2ex_hwcrypto API for hash calculation. This change will open hardware
crypto acceleration up to all hash calculations in coreboot (most
notably CBFS verification). As part of this change, the
vb2_digest_buffer() function has been removed, so replace existing
instances in coreboot with the newer vb2_hash_calculate() API.

Due to the circular dependency of these changes with vboot, this patch
also needs to update the vboot submodule:

Updating from commit id 18cb85b5:
    2load_kernel.c: Expose load kernel as vb2_api

to commit id b827ddb9:
    tests: Ensure auxfw sync runs after EC sync

This brings in 15 new commits.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-09-02 23:51:29 +00:00
Hsin-Te Yuan cb28d649ea x86/cache.c: Implement dcache_*
A new ChromeOS automated test will be introduced to check the cbmem log
of diagnostic boot mode. Because the diagnostic boot does not allow
booting into kernel, the test must perform AP reset and then check the
cbmem log afterwards. However, the memory content might not be written
back to memory (from CPU cache) during AP reset because of the cache
snooping mechanism on x86. Hence, some API to flush cache is needed.

Implement dcache_* to allow flushing cache proactively in x86. To avoid
unnecessary flush, check dma_coherent before calling dcache_* functions,
which will be always true in x86. Therefore, this change won't affect
the original functionality.

BUG=b:190026346
TEST=FW_NAME=primus emerge-brya libpayload

Cq-Depend: chromium:3841252
Signed-off-by: Hsin-Te Yuan <yuanhsinte@google.com>
Change-Id: I622d8b1cc652cbe477954a900885d12e6494d94d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-01 14:21:11 +00:00
Yu-Ping Wu 30d8e724e7 libpayload: Add const for dma_coherent argument
Add the const modifier for the ptr argument of dma_coherent to avoid
unnecessary type casting in payloads.

BUG=none
TEST=emerge-corsola libpayload
BRANCH=none

Change-Id: Ic4bb1d8318c7e83fd3ab3054aa0333cb27afe588
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Hsin-Te Yuan <yuanhsinte@google.com>
2022-08-24 21:27:46 +00:00
Jon Murphy c4e90454f4 treewide: Unify Google branding
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).

This CL also includes changing Chromium OS to ChromiumOS as well.

BUG=None
TEST=N/A

Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-04 14:02:26 +00:00
Hsuan Ting Chen 607b39c593 libpayload: Add commonlib/bsd/elog and its dependency
Add commonlib/bsd/elog dependency in libpayload. This will allow other
payloads (e.g. depthcharge) to implement their own eventlog read and
write utilities.

Also include commonlib/bsd/elog.c source to libc-srcs. This ensure
payloads could utilize commonlib elog helper functions.

Change-Id: I64d0fdd2a8eff1d89a1ac451d37b61787b5564e7
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-09 13:33:35 +00:00
Julius Werner 23d2465720 commonlib: Clean up compiler.h
This patch contains several minor cleanups related to compiler.h:

- Replace __always_unused() (which is a Linux-specific concept that
  doesn't make sense without also having __maybe_unused(), and had zero
  uses in the codebase) with __unused() which moves here from helpers.h

- Add __underscores__ to the names of all attributes in the compiler
  attribute shorthand macros. This is necessary to make them work in
  files where the same name was already used for an identifier (e.g.
  cbfstool/cbfs.h's `unused` array of file types).

- Remove libpayload's own copy of compiler.h and make it directly pull
  in the commonlib/bsd copy.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I9644da594bb69133843c6b7f12ce50b2e45fd24b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-06-07 12:34:35 +00:00
Jianjun Wang 2ad74deb2a libpayload/pci: Add support for bus mapping
Move the common APIs to pci_ops.c and IO based operations to
pci_io_ops.c, and add pci_map_bus_ops.c to support bus mapping.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-05-20 02:51:33 +00:00
Jianjun Wang d16c2aa6de coreboot_tables: Add PCIe info to coreboot table
Add 'lb_fill_pcie' function to pass PCIe information from coreboot to
libpayload, and add CB_ERR_NOT_IMPLEMENTED to the cb_err enum for the
__weak function.

ARM platform usually does not have common address for PCIe to access the
configuration space of devices. Therefore, new API is added to pass the
base address of PCIe controller for payloads to access PCIe devices.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
2022-05-19 16:34:55 +00:00
David Hendricks 7d0e5fa3ff libpayload: Fix guards in include/{arm,arm64,x86}/arch/barrier.h
Change-Id: Ib4897c4f5837f7f3173d5062eecb893adbe36964
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-16 06:55:06 +00:00
Jianjun Wang b2537bdad5 coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_t
Replace 'struct lb_uint64' with 'typedef __aligned(4) uint64_t
lb_uint64_t', and remove unpack_lb64/pack_lb64 functions since it's no
longer needed.

Also replace 'struct cbuint64' with 'cb_uint64_t' and remove
'cb_unpack64' in libpayload for compatible with lb_uint64_t.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-14 22:27:50 +00:00
Jakub Czapiga 9760264a96 commonlib/bsd/helpers: Remove redundancy with libpayload defines
Move STRINGIFY() from coreboot string.h to commonlib/bsd/helpers.h
Remove redundant defines from libpayload.h and libpayloads' standard
headers.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I3263b2aa7657759207bf6ffda750d839e741f99c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-30 21:21:47 +00:00
Arthur Heymans cddba4528d libpayload: Parse the ACPI RSDP table entry
Change-Id: I583cda63c3f0b58f8d198ed5ecea7c4619c7a897
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30 00:03:28 +00:00
Ravi Kumar Bokka 42fcb2a8f4 libpayload: Parse DDR Information using coreboot tables
BUG=b:182963902,b:177917361
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59193
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-16 01:21:44 +00:00
Julius Werner 69cc557cfb commonlib/bsd: Remove cb_err_t
cb_err_t was meant to be used in place of `enum cb_err` in all
situations, but the choice to use a typedef here seems to be
controversial. We should not be arbitrarily using two different
identifiers for the same thing across the codebase, so since there are
no use cases for serializing enum cb_err at the moment (which would be
the primary reason to typedef a fixed-width integer instead), remove
cb_err_t again for now.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09 02:18:21 +00:00
Julius Werner db29b3765b libpayload: Fix legacy CBFS code after recent refactoring
The goal when adding the new CBFS API in CB:59497 was that the old CBFS
code would be left completely untouched and just moved to the side a
bit, so that it could continue to work for the payloads that use it
until they all have time to transition to the new CBFS API.
Unfortunately, between the different iterations of the patch something
went wrong with that and the final committed version of cbfs_legacy.c
does differ in some parts from the original code, including a changed
macro definition that breaks decompression support. This patch restores
all the legacy CBFS files to exactly what they used to be (other than
the necessary changes in cbfs_core.h to avoid double definition
clashes).

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ic7fd428acb03d3830f66f807cd1d7cdbd652f409
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-01-14 00:41:13 +00:00
Jakub Czapiga ad45f681aa libpayload/libcbfs: Add unverified_area APIs
This patch introduces equivalents of unverified_area CBFS access
functions added to the main coreboot tree in CB:59678

Change-Id: Ibadfd2a5cb6ad037ef1222b0a4301f90a79a127b
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-12 16:15:59 +00:00
Jakub Czapiga 63e54275f6 libpayload: Implement new CBFS access API
This commit adds new CBFS API, which is based on the one available in
the main coreboot source tree. Libpayload implementation supports RO/RW
file lookups and file contents verification.

Change-Id: I00da0658dbac0cddf92ad55611def947932d23c7
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-01-10 14:30:04 +00:00
Jakub Czapiga 8fac662f30 libpayload/libc/fmap: Implement new FlashMap API
This patch introduces new FlashMap API, the fmap_locate_area().
It works on cached FlashMap provided in lib_sysinfo.fmap_cache.

Change-Id: Idbf9016ce73aa58e17f3ee19920ab83dc6c25abb
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-23 14:37:42 +00:00
Jianjun Wang 8bb59ca2fa lib: Add __fls() (Find Last Set)
Implement __fls() as an alias for log2(), and remove the duplicate
definitions in commonlib/storage/sdhci.c.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ib458abfec7e03b2979569a8440a6e69b0285ac32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-13 02:57:07 +00:00
Jakub Czapiga f7d6eb2fef libpayload: Add boot_device_read() function
This patch adds a new way of implementing flash access for libpayload.
Until now all reads had to be performed using cbfs_media, which is
obsolete. From now on all reads should be performed using
boot_device_read().

This patch also provides a default implementation of boot_device_read()
for x86 architecture.

Change-Id: I1babd2a8414ed9de3ca49903fcb4f036997b5ff3
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-10 17:56:34 +00:00
Jakub Czapiga 2f236c232d libpayload: Add CBMEM_IMD_ENTRY support to coreboot tables parser
coreboot stores much information in the CBMEM IMD. Until now it was
ignored. This patch makes use of these coreboot tables entries.
It also removes get_cbmem_addr() function as it is no longer needed.

Moreover, the coreboot tables entry CB_TAG_MRC_CACHE does not exist
anymore, as it is not created by the code. It was replaced by
CBMEM_ID_MRCDATA entry, so MRCDATA should now be accessible through
sysinfo structure field.

Change-Id: I5bd02a98ba2631f34014bc0f8e7ebd5a5ddd2321
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-03 16:51:41 +00:00
Jakub Czapiga c69ea3285e libpayload: Add mock assert support for unit testing purposes
Some unit tests might require catching assert failures. This patch adds
an assert() variant depending on __TEST__ define passed to unit tests.

Change-Id: I7e4620400f27dbebc57c71bbf2bf9144ca65807f
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-23 23:38:15 +00:00
Jakub Czapiga 111de557ee tests: Move x86 I/O functions to include/mock/arch/io.h
Move th x86 I/O functions declarations from tests mocks to the mock
architecture io.h. This will make x86 I/O-dependent tests simpler,
because the x86_io.h from mocks will not have to be included manually.

Change-Id: Ie7f06c992be306d2523f2079bc90adf114b93946
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-04 15:07:38 +00:00
Jakub Czapiga 3d91b47b42 libpayload: Add mock architecture
Mock architecture can be used to build libpayload using host compiler.
It can be enabled by setting ARCH_MOCK=y in the dotconfig. It sets
LITTLE_ENDIAN=y, as most machines these days use little-endian CPUs.
Libpayload will use HOSTCC as CC, HOSTLD as LD, etc. instead of tools
provided by xcompile.
Mock architecture configuration can be used by payloads for testing
purposes. Thanks to it, tests can be architecture-independent,
and can be executed without requiring compatible Kconfig options,
e.g. ARCH_ARM64=y for ARM64 machine. However, one has to provide
implementation for most architecture-specific functions present
in arch/* directories.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ie3a6e6f6cad2f8a2e48a8e546d3b79c577653080
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-10-11 12:59:57 +00:00
Nick Vaccaro 15066ba8d4 driver/intel/pmc_mux/conn: Move typec_orientation enum to coreboot_tables.h
Move the locally declared typec_orientation enum from chip.h to
coreboot_tables.h.

Change enum typec_orientation name to type_c_orientation for consistency
with contents of coreboot_tables.h.

Rename TYPEC_ORIENTATION_FOLLOW_CC to TYPEC_ORIENTATION_NONE.

BUG=b:149830546
TEST="emerge-volteer coreboot" and make sure it compiles successfully.

Change-Id: I24c9177be72b0c9831791aa7d1f7b1236309c9cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-10-04 17:15:47 +00:00
Nick Vaccaro a62b41819c coreboot tables: Add type-c port info to coreboot table
This change adds type-c port information for USB Type-C ports to the
coreboot table.  This allows depthcharge to know the usb2 and usb3
port number assignments for each available port, as well as the SBU
and data line orientation for the board.

BUG=b:149830546
TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds
successfully.  Cherry-pick CL to enable this feature for volteer,
flash and boot volteer2 to kernel, log in and check cbmem for type-c
info exported to the payload:
  localhost ~ # cbmem -c | grep type-c
  added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0
  added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0

Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-04 17:12:48 +00:00
Julius Werner ea03d0047b device/mmio: Make buffer_to_fifo32() take a const buffer
The input buffer to the buffer_to_fifo family of functions is only read,
so it can be a const pointer. (Also, remove the MIPS check in libpayload
for these functions... the MIPS architecture has been removed a while
ago.)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I021069680cf691590fdacc3d51f747f12ae3df31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-09-20 12:07:51 +00:00
Furquan Shaikh bda86bd497 nvs: Add Chrome OS NVS (CNVS) information to coreboot tables
CB:51638 separated Chrome OS NVS from global NVS by allocating it
separately in CBMEM. CNVS is used in depthcharge to fill firmware
information at boot time. Thus, location of CNVS needs to be shared in
coreboot tables for depthcharge to use.

This change adds a new coreboot table tag
`CB_TAG_ACPI_CNVS`/`CB_TAG_ACPI_CNVS`(0x41) which provides the
location of CNVS in CBMEM to payload (depthcharge).

Additionally, CB:51639 refactored device nvs(DNVS) and moved it to the
end of GNVS instead of the fixed offset 0x1000. DNVS is used on older
Intel platforms like baytrail, braswell and broadwell and depthcharge
fills this at boot time as well. Since DNVS is no longer used on any
new platforms, this information is not passed in coreboot
tables. Instead depthcharge is being updated to use statically defined
offsets for DNVS.

BUG=b:191324611, b:191324611
TEST=Verified that `crossystem fwid` which reads fwid information from
CNVS is reported correctly on brya.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3815d5ecb5f0b534ead61836c2d275083e397ff0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55665
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 18:38:14 +00:00
Nico Huber 358c84a5a8 includes: Move *abs() declarations into `stdlib.h`
Change-Id: Id4df2d3210735bee737353d293450e59cf93bd9a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55593
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:39:26 +00:00
Nico Huber c538ce12ae includes: Remove dangling doxygen @}
Change-Id: I05e02f9689c1a6dafb3943657a3db975c2aeacbe
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55592
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:38:50 +00:00
Nico Huber c1536adcf4 includes: Define `CHAR_BIT` in `limits.h`
Change-Id: Ib1d80d0c7457f90596ef5cd9d5ad0c4a33c8d473
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55591
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:38:33 +00:00
Nico Huber 2eae410c54 includes: Provide `wchar.h` with `wchar_t` and `wint_t`
Change-Id: Iacb0e4eaf3f0b6bf843f3bfda5bdfde0f7a98808
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55590
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:38:16 +00:00
Nico Huber 0a31d5e7f5 includes: Add include guards to `stddef.h`
Change-Id: Ifae4f07abd75da9784967c2020eed2c3fe64afa0
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55589
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18 04:37:18 +00:00
Thomas Heijligen fffc21d3dc libpayload/storage: Add NVMe driver
Tested with qemu virtual NVMe and Intel hardware. Works with FILO.

Change-Id: Ie75b1dc743dac3426c230c57ee23b771ba3a6e0c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33582
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-07 10:58:04 +00:00
Patrick Georgi 9de060fd34 libpayload: Use volatile pointers in {read,write}{8,16,32,64}
This is already the case on x86 but not on the ARM platforms, and
{read,write}[bwl] are using volatile pointers, too, so follow suit.

Change-Id: I6819df62016990e12410eaa9c3c97b8b90944b51
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-20 17:01:09 +00:00
Patrick Georgi 60f5328c7d libpayload/arm*: Add 64bit memory access primitives
Add read64 and write64 for consistency with x86.

BUG=b:178785769

Change-Id: I342e3a23201d0b804ea5ecfe47ee3e4bb516de4c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-30 20:17:47 +00:00
Nico Huber 4f7b687fb7 libpayload/i8042: Add API to peek on keyboard input queue
Change-Id: I60699e044b5bacd3f5292fed7edbf529ae133284
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47592
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24 08:29:18 +00:00
Nico Huber 0e1d19baa6 libpayload/i8042: Add API to get/set kbd translation state
Change-Id: I49aa1c244cb60ea290df102f06f641c765f59fa5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-23 03:29:16 +00:00
Furquan Shaikh 493937e1d6 coreboot tables: Add SPI flash memory map windows to coreboot tables
This change adds details about the memory map windows to translate
addresses between SPI flash space and host address space to coreboot
tables. This is useful for payloads to setup the translation using the
decode windows already known to coreboot. Until now, there was a
single decode window at the top of 4G used by all x86
platforms. However, going forward, platforms might support more decode
windows and hence in order to avoid duplication in payloads this
information is filled in coreboot tables.

`lb_spi_flash()` is updated to fill in the details about these windows
by making a call to `spi_flash_get_mmap_windows()` which is
implemented by the driver providing the boot media mapping device.

BUG=b:171534504

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I00ae33d9b53fecd0a8eadd22531fdff8bde9ee94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48185
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08 22:56:09 +00:00
Meng-Huan Yu c9655468e8 libpayload: Provide API to expose MMU memery ranges for ARM64
Provide get_mmu_ranges() for ARM64 to let payloads could get
MMU ranges for all used memory regions.

BUG=b:171858277
TEST=Build in x86, arm, arm64.
  emerge-zork libpayload depthcharge
  emerge-nyan libpayload depthcharge
  emerge-asurada libpayload depthcharge

Signed-off-by: Meng-Huan Yu <menghuan@google.com>
Change-Id: I39b24aefc9dbe530169b272e839d0e1e7c697742
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-05 09:45:34 +00:00
Caveh Jalali 6de5bf6698 libpayload/usb: Add format string checking to usb_debug
This turns on the compiler's printf style format string checker.

BUG=b:167517417
TEST=enabled all USB controllers on volteer and fixed resulting
	compiler errors when USB_DEBUG is enabled.

Change-Id: Ic94ebcbafdde8a5f79278b5635111b99af40f892
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45025
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 22:34:55 +00:00
Jacob Garber c98baa7a80 libpayload: Add compiler.h to compiler parameters
Headers in libpayload define various structs like so:

    struct struct_name { ... } __packed;

However, these header files do not include the compiler.h macro that
defines what __packed is, so they are actually defining a variable named
__packed and *not* declaring a packed struct. This leads to defining the
same variable multiple times, which was caught by GCC 10. Add compiler.h
to the compiler parameters so it is included in all files automatically.

Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ia67182520dc94149e06fe9e03a14b3fc2ee29973
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-08 11:37:04 +00:00
Nico Huber 5c9d82bd73 libpayload/x86: Add enumeration of Intel family 6 models
The list is incomplete and only contains what we need in the follow-up
commit. It can be extended at will.

Change-Id: Ibf8ddaf510eb513ee74af3e78da46b04802a91b9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-02 06:24:10 +00:00
Tim Wawrzynczak e1a7a26f5e lib/libpayload: Replace strapping_ids with new board configuration entry
There are currently 3 different strapping ID entries in the coreboot
table, which adds overhead. The new fw_config field is also desired in
the coreboot table, which is another kind of strapping id. Therefore,
this patch deprecates the 3 current strapping ID entries (board ID, RAM
code, and SKU ID), and adds a new entry ("board_config") which provides
board ID, RAM code, SKU ID, as well as FW_CONFIG together.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1ecec847ee77b72233587c1ad7f124e2027470bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-30 15:25:28 +00:00
Nico Huber d9e543a5f9 libpayload/keyboard: Use `bool` as return type
Use `bool` whenever `0` was used to indicate an error. The mixing of
different types for return values was mildly confusing and potentially
dangerous with the i8042 API close by that uses `0` for success.

Change-Id: I876bb5076c4921f36e3438f359be8ac4c09248cc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:57:47 +00:00
Nico Huber bfa46e25e0 libpayload: Add <stdbool.h>
Change-Id: I972c78c5da4136bc61e78fcbb52d7d162cc1b698
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26 06:57:06 +00:00