Extend the generic flash interface to probe for write protected regions.
Add Winbond custom code to return flash protection.
Tested on Cavium EVB CN81xx using W25Q128.
Change-Id: I933a8abdc28174ec32acf323c102d606b58c1ea5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25082
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make XBCM `Serialized` (obvious), and check for the callee clearing the
request bit (we checked only the status for 0 which we potentially wrote
ourselves).
Change-Id: Ic92d525eda8d0a159fa5ddaacf230658d71c1578
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The device tree now supports 'hidden' and the status can be found in
`struct device.hidden`. A new acpi_device_status() will return the
expected setting of STA from a `struct device`.
BUG=b:72200466
BRANCH=eve
TEST=Builds and boots properly on device eve
Change-Id: I6dc62aff63cc3cb950739398a4dcac21836c9766
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28567
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For devices supporting both Linux and Windows, we may find some ACPI
devices that only need drivers in Linux and should not even be shown in
Windows Device Manager UI.
The new 'hidden' keyword in device tree 'device' statement allows
devices sharing same driver to call acpi_gen_writeSTA with different
values.
BUG=b:72200466
BRANCH=eve
TEST=Builds and boots properly on device eve
Change-Id: Iae881a294b122d3a581b456285d2992ab637fb8e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
XS is a read-only field of mstatus. Unable to be write. So remove this code.
Change-Id: I3ad6b0029900124ac7cce062e668a0ea5a8b2c0e
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28357
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set up EMMC gpios for payloads.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I1e7ee9bfe3a26ed04374e8c74243f48552a1d254
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
As we don't use the MIPI camera on Rammus, disable SA Imaging Unit and
CIO2 devices to avoid the system failed to enter S0ix.
BUG=b:114502527
BRANCH=master
TEST=On DUT, echo freeze > /sys/power/state
1. check the S0ix status on EC console
2. check the value of /sys/kernel/debug/pmc_core/slp_s0_residency_usec
Change-Id: I91629732db01ee534f0ddb67a2b358d725ef810e
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We have a pin from AP to EC, called AP_IN_SLEEP_L (SRCLKENA0 on AP side,
pad R23) that is supposed to be high in S0, and low in S3 (and X/don't
care in S5).
This should be set as early as possible in bootblock.
BUG=b:113367227
TEST=make; boots and verified AP_IN_SLEEP_L GPIO is high.
BRANCH=None
Change-Id: Icd59fa366c162e7443b8932a851e65f110f551ab
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@google.com>
Turn on SOC_INTEL_CANNONLAKE_MEMCFG_INT for coffeelake rvp platform
for easier collabration on newer platform. The setting in memory.c get
from board design itself.
BUG=N/A
TEST=Build and boot up with whiskey lake rvp platform.
Change-Id: I10f3af4bed511153cef4d6f3a93caea57cc4ae90
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28257
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch sets the MRC UPD CmdTriStateDis for the atlas boards.
Atlas is a LPDDR3 design without RTT for CMD/CTRL.
The original change for
nocturne is I0f593761dcbd121e7e758421af178931b9d78295
mb/google/poppy: Set UPD CmdTriStateDis for Nocturne
BUG=b:111812662
Change-Id: I45b6dd22412c689c8db64f4650e9fa9e87dec2ec
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
At ECC 2017 user Bob reports, that an image built for the Lenovo T500
runs on the Lenovo W500 without any issues.
Change-Id: I17fd9725ab85ba2f0c99a70f40e35432265a81c1
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/22226
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ram_resource is board specific and should be moved there.
Change-Id: I50bd9aaaae39422e565d8bf205a6365c59299df0
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
There are 8 possible BERT context errors, with table ctx_names being a
table to print their names. Thus the table is supposed to have 8 elements,
and indeed it has 8 lines... but some lines are missing commas, and when
compiling it becomes a 5 element table. Add the commas at the appropriate
places.
BUG=b:115719190
TEST=none.
Change-Id: I04a2c82a25fe5f334637053ef81fa6daffb5b9c5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
On the FU540 the bootblock runs on a core without lesser privilege
modes, so the medeleg/mideleg CSRs are not implemented on that core,
leading to a CPU exception when these CSRs are accessed.
Configure medeleg/mideleg only if the misa register indicates that
S-mode is implemented on the executing RISC-V core.
Change-Id: Idad97e42bac2ff438dd233a5d125f93594505d63
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25791
Reviewed-by: Xiang Wang <wxjstz@126.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Iteration over devices in add_ivrs_device_entries were simplified to
decrease complexity.
- Code was structured to satisfy checkpatch
Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/15164
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CBLV is not kept up to date by Linux' i915. We should fix that too,
but it will likely take some years until we can always expect it to
work.
For now read the register values directly. To accomodate that we
are not the only one writing those, revise XBQC() to search for
the closest value in BRIG (instead of a lower equal one) and round
more accurately for better matches.
Change-Id: I4e2d8fa34e75463d4cf7242af3e2c67577cfa2a5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Only execute coreboot on hart 0 until synchronisation between hart's is ready.
Change-Id: I2181e79572fbb9cc7bee39a3c2298c0dae6c1658
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Mainly update headers to build.
Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove
function configuring the global reset through PMC base.
On denverton the global reset lock is not in PMC base
but in the PCI registers so this code cannot be shared.
Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/25426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Evandro Luiz Hauenstein <kingsumos@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
The pmh7 has at least a 9bit address space.
The h8s allows to access the 9th address space by using io port
0x15ed as second address register.
The pmh7 is connected via SPI to the h8s. The h8s is acting as
proxy to access the address space.
Change-Id: I0d7ce00950862adf928a88d70afbc33df8b87d9a
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/28196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Evgeny Zinoviev <me@ch1p.com>
After changing clock from 33.33Mhz to 1Ghz the UART divisor needs to be
recalculated. Return correct tlck frequency in uart_platform_refclk.
Change-Id: I2291e4198cf466a8334211c6c46bc3268fc979a9
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Based on SiFive bootloader code
Change-Id: I71043ce9e458e25e64da28d53cd36b02d2e22acc
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28604
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Invoke clock_init in romstage for SiFive Unleashed.
Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The RISC-V Privileged Architecture specification defines the Machine
Time Registers (mtime and mtimecmp) in section 3.1.15.
Makes it possible to use the generic udelay.
The timer is enabled using RISCV_USE_ARCH_TIMER for the lowrisc,
sifive and ucb soc.
Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27434
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add original files from SiFive bootloader.
Change-Id: I8beb75c070a6fac1700dd7644fc4fe9df226e716
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The board version is part of EC's EEPROM, but is not being populated
from EEPROM. Instead a default Kconfig parameter is returned as board
version. Select GOOGLE_SMBIOS_MAINBOARD_VERSION Kconfig item to enable
requesting the EC for board version.
BUG=b:114001972,b:114677884,b:114677887
Change-Id: Ib404a9da35156e197d232088fd7ca69432effbca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/28539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Make it uniform as other architectures also include it in io.h
Change-Id: I62c2d909c703f01cdaabdaaba344f82b6746f094
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28601
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This modification for DVT build and use CBI method
enable all memory particles.
BUG=b:112870780
TEST=verify it under the EVT unit and pre-test EVT
unit(rework RAM ID follow the proposal) respectively.
Change-Id: I488a0652ba348eff9a6d8591b0cfa6ed4fe808aa
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a __always_inline macro that wraps __attribute__((always_inline))
and replace current users with the macro, excluding files under
src/vendorcode.
Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/28587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@google.com>
The documentation unfortunately doesn't match what SiFive uses in their FSBL.
Use the same values as in FSBL to make DDR RAM work.
Change-Id: I844cc41ed197333adeae495e71ea70b4a9603650
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/28582
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SiFive UART on the HiFive Unleashed uses the tlclk as input clock
which runs at coreclk / 2.
The input frequency is configured in the board code depending on the
current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz)
Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid
Inter Flash Descriptor to exist. It does *not* identify platforms or boards
that are capable of running in descriptor mode if it's valid.
Refine the help text to make this clear.
Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply
declare that IFD is supported by the platform. Select this value everywhere
instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to
y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected.
Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to
the mainboard directory.
Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Only for those that are x86 and also have a RW_LEGACY region.
The assumption is that all devices touched have 64k block sizes when
choosing size and alignment of the region.
Change-Id: I12addb137604f003d1296f34f555dae219330b18
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of gpio_num, gpio_address should be used as the address in
write32. This lets us also get rid of a few casts.
Commit c9ed3ee8d8 ("soc/amd/stoneyridge: Fix gpio_set function") fixed
one instance of this bug, but it was more widespread.
TEST=None
Change-Id: I0cf87aac2f1b87b6eac2b506515e48fe908c1f2b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Add a duplicate ACPI_BERT symbol with a 'y' default setting and additional
help text.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I817111cbd3e81b93d8b02d0654ba68c8678b1bbe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Expand the BERT reserved region size setting to account for the
possibility of no TSEG configuration. This change is only for
completeness, as stoneyridge must always use TSEG.
Change-Id: I90753fa408cfac4de38aff08979c45349bb62a66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Currently, there is a trailing space in the log message below.
> Enabling VR PS2 mode: VNN VCC
So, put the space before the word.
Change-Id: Ic536d77aa910b1b98a3c2f35d595dee4251b1c18
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/28525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Patrick Rudolph